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PDF MAX13483E Data sheet ( Hoja de datos )
| Número de pieza | MAX13483E | |
| Descripción | (MAX13481E - MAX13483E) ESD-Protected USB Transceivers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3801; Rev 2; 1/06
www.DataSheet4U.com
±15kV ESD-Protected USB Transceivers with
External/Internal Pullup Resistors
General Description
The MAX13481E/MAX13482E/MAX13483E ±15kV ESD-
protected USB-compliant transceivers interface low-
voltage ASICs with USB devices. The transceivers fully
comply to USB 2.0 when operating at full-speed
(12Mbps). The transceivers also operate with VL as low
as 1.6V, ensuring compatibility with low-voltage ASICs.
The MAX13481E/MAX13482E/MAX13483E feature a
logic-selectable suspend mode that reduces current
consumption. Integrated ±15kV ESD circuitry protects
D+ and D- bus connections.
The MAX13481E/MAX13482E/MAX13483E operate over
the extended -40°C to +85°C temperature range and are
available in a 16-pin (3mm x 3mm) thin QFN package.
Applications
Cell Phones
PDAs
Digital Still Cameras
Selector Guide
PART
MAX13481EETE
MAX13482EETE
MAX13483EETE
ENUM
INPUT
✓
✓
—
INTERNAL
1.5kΩ
RESISTOR
—
✓
—
VBUS
DETECTION
—
✓
✓
Typical Operating Circuits appear at end of data sheet.
TOP VIEW
Features
♦ Active-Low Enumeration Input Controls D+ Pullup
Resistor (MAX13482E)
♦ Active-Low Enumeration Input Controls Internal
Pullup Switch (MAX13481E)
♦ ±15kV ESD Protection on D+ and D-
♦ USB 2.0 Full-Speed Compliant Transceiver
♦ VBUS Detection (MAX13482E/MAX13483E)
♦ +1.60V to +3.6V VL Allows Connection with Low-
Voltage ASICs
♦ No Power-Supply Sequencing Required
♦ Pin Compatible with MIC2551A (MAX13481E)
♦ Pin Compatible with DP1680 (MAX13483E)
♦ Pin Compatible with DP1681 (MAX13481E)
♦ Pin Compatible with DP1682 (MAX13482E)
Ordering Information
PART
PIN-PACKAGE
TOP
MARK
MAX13481EETE 3mm X 3mm TQFN-EP*
MAX13482EETE 3mm X 3mm TQFN-EP*
MAX13483EETE 3mm X 3mm TQFN-EP*
ADF
ADI
ADJ
*EP = Exposed Paddle.
PKG
CODE
T1633-4
T1633-4
T1633-4
Pin Configurations
VPU (VPUR) 13
VBUS 14
VL 15
N.C. (BD) 16
12 11 10 9
*EP
MAX13481E
MAX13482E
1234
8 N.C.
7 SUS
6 GND
5 ENUM
12 11 10 9
I.C. 13
VBUS 14
VL 15
*EP
MAX13483E
8 N.C.
7 SUS
6 GND
BD 16
5 N.C.
1234
( ) MAX13482E ONLY
TQFN
3mm x 3mm
*EXPOSED PADDLE
TQFN
3mm x 3mm
*EXPOSED PADDLE
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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±15kV ESD-Protected USB Transceivers with
External/Internal Pullup Resistors
Typical Operating Characteristics (continued)
(VBUS = 5V, VL = +3.3V, TA = +25°C, unless otherwise noted.)
SINGLE-ENDED RECEIVER PROPAGATION
DELAY vs. TEMPERATURE
5
4
3
2
1
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
VBUS SUSPEND CURRENT
vs. VBUS
20
19 TA = +25°C
TA = +85°C
18
17
16 TA = -40°C
15
14
13
4.0 4.3 4.6 4.9 5.2 5.5
VBUS (V)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
TRANSMITTER SKEW
vs. TEMPERATURE
-15 10 35 60
TEMPERATURE (°C)
85
VBUS SUPPLY CURRENT
vs. D+/D- CAPACITANCE
18
16
14
12
10
8
6
4
2
0
0 10 20 30 40 50 60 70 80 90 100
CAPACITANCE (pF)
VL SUSPEND CURRENT
vs. TEMPERATURE
100
10
1
0.1
0.01
-40
-15 10 35 60
TEMPERATURE (°C)
85
VL SUPPLY CURRENT
vs. D+/D- CAPACITANCE
1.50
1.45
1.40
1.35
1.30 VL = 2.5V
1.25
1.20
1.15
1.10 VL = 1.8V
1.05
1.00
0 10 20 30 40 50 60 70 80 90 100
CAPACITANCE (pF)
TRANSMIT MODE (OE = LOW)
MAX13481E toc10
VP
1V/div
VM
D+
10ns/div
1V/div
D-
RECEIVE MODE (OE = HIGH)
MAX13481E toc11
D+
1V/div
D-
RCV
1V/div
10ns/div
SUSPEND MODE
MAX13481E toc12
SUS
2V/div
20ns/div
D+
2V/div
D-
RCV
2V/div
_______________________________________________________________________________________ 5
5 Page 
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±15kV ESD-Protected USB Transceivers with
External/Internal Pullup Resistors
Timing Diagrams
VOHD
tFR, tLR
90%
tFF, tLF
90%
10%
VOLD
Figure 1. Rise and Fall Times
10%
OE
D+/D-
VP/VM CONNECTED TO GND,
D+/D- CONNECTED
TO PULLUP
tPLZ_DRV
VP AND VM RISE/FALL TIMES < 4ns
VM
OE
VP
tPLH_DRV
tPHL_DRV
D-
VCRS_F , VCRS_L
D+
D+/D-
tPHZ_DRV
tPZL_DRV
VP/VM CONNECTED TO VL,
D+/D- CONNECTED
TO PULLDOWN
tPZH_DRV
Figure 2. Timing of VP and VM to D+ and D-
stand voltage measured to IEC 61000-4-2 generally is
lower than that measured using the Human Body
Model. Figure 8 shows the IEC 61000-4-2 model. The
Contact Discharge method connects the probe to the
device before the probe is charged.
Machine Model
The Machine Model for ESD tests all connections using
a 200pF storage capacitor and zero discharge resis-
Figure 3. Driver’s Enable and Disable Timing
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just inputs and outputs. After PC
board assembly, the Machine Model is less relevant to
I/O ports.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MAX13483E.PDF ] | |
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