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PDF FAN7385 Data sheet ( Hoja de datos )
| Número de pieza | FAN7385 | |
| Descripción | Dual-Channel High-Side Gate-Drive IC | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN7385
Dual-Channel High-Side Gate-Drive IC
February 2007
Features
Floating Channel for Bootstrap Operation to +600V
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VDD=VBS=15V
High-Side Output In-Phase of Input Signal
VDD & VBS Supply Range from 10V to 20V
3.3V and 5V Input Logic Compatible
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for Both Channels
Applications
Normal Half-Bridge and Full-Bridge Driver
PDP Energy Recovery Switch Control Driver
Switching Mode Power Supply
Description
The FAN7385 is a monolithic high side gate drive IC
designed for high voltage, high speed driving MOSFETs
and IGBTs operating up to +600V.
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS = -9.8V (typical) for VBS = 15V.
The UVLO circuits prevent malfunction when VBS1 and
VBS2 are lower than the specified threshold voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for dual high-side switches
and half-bridge inverters.
14-SOP
1
Ordering Information
Part Number
Package
Pb-Free
Operating Temperature
Range
FAN7385M(1)
FAN7385MX(1)
14-SOP
Yes
-40°C ~ 125°C
Note:
1. These devices passed wave soldering test by JESD22A-111.
Packing Method
Tube
Tape & Reel
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Parameter
Min.
Max.
Unit
VS
VB
VHO
VDD
VIN
GND
dVS/dt
PD(2)(3)(4)
θJA
TJ
TS
High-side offset voltage VS1 ,VS2
High-side floating supply voltage VB1 ,VB2
High-side floating output voltage HO1, HO2
Low-side and logic-fixed supply voltage
Logic input voltage (IN1, IN2)
Logic ground
Allowable offset voltage slew rate
Power dissipation
Thermal resistance, junction-to-ambient
Junction temperature
Storage temperature
VB-25
-0.3
VS-0.3
-0.3
-0.3
VDD-25
VB+0.3
625
VB+0.3
25
VDD+0.3
VDD+0.3
50
1.0
110
150
150
V
V
V
V
V
V
V/ns
W
°C/W
°C
°C
Notes:
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VB
VS
VDD
VHO
VIN
TA
Parameter
High-side floating supply voltage
High-side floating supply offset voltage
Supply voltage
High-side (HO1, HO2) output voltage
Logic input voltage (IN1, IN2)
Ambient temperature
Condition
Min.
VS+10
6-VDD
10
VS
GND
-40
Max.
VS+20
600
20
VB
VDD
125
Unit
V
V
V
V
V
°C
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
5
www.fairchildsemi.com
5 Page 
Typical Characteristics (Continued)
50
40
30
20
10
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 30. Falling Time vs. Supply Voltage
160
150
140
130
120
110
100
90
80
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 31. Turn-On Delay Time vs. Supply Voltage
160
150
140
130
120
110
100
90
80
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 32. Turn-Off Delay Time vs. Supply Voltage
500
450
400
350
300
250
200
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 33. Output Source Current vs. Supply Voltage
1000
900
800
700
600
500
400
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 34. Output Sink Current vs. Supply Voltage
-4
-6
-8
-10
-12
-14
-16
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 35. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Supply Voltage
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet FAN7385.PDF ] | |
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