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PDF M25PE20 Data sheet ( Hoja de datos )
| Número de pieza | M25PE20 | |
| Descripción | (M25PE10 / M25PE20) Page-Erasable Serial Flash Memories | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M25PE20
M25PE10
1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories
with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out
FEATURES SUMMARY
■ Industrial Standard SPI Pin-out
■ 1 or 2 Mbit of Page-Erasable Flash Memory
■ Page Write (up to 256 Bytes) in 11ms (typical)
■ Page Program (up to 256 Bytes) in 1.2ms
(typical)
■ Page Erase (256 Bytes) in 10ms (typical)
■ Sector Erase (512 Kbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 33MHz Clock Rate (maximum)
■ Deep Power-down Mode 1µA (typical)
■ Electronic Signature
– JEDEC Standard Two-Byte Signature
(8012h for M25PE20
8011h for M25PE10)
■ More than 100,000 Write Cycles
■ More than 20 Year Data Retention
■ Hardware Write Protection of the Top Sector
(64KB)
■ Packages
– ECOPACK® (RoHS compliant)
Figure 1. Packages
VDFPN8 (MP)
6x5mm (MLP8)
8
1
SO8N (MN)
150 mil width
October 2005
1/37
1 page  
M25PE10, M25PE20
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is
not the Deep Power-down mode). Driving Chip
Select (S) Low selects the device, placing it in the
Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter the Reset
mode. In this mode, the output is high impedance.
Driving Reset (Reset) Low while an internal oper-
ation is in progress will affect this operation (write,
program or erase cycle) and data may be lost.
Top Sector Lock (TSL). This input signal puts
the device in the Hardware Protected mode, when
Top Sector Lock (TSL) is connected to VSS, caus-
ing the top 256 pages (upper addresses) of the
memory to become read-only (protected from
write, program and erase operations).
When Top Sector Lock (TSL) is connected to VCC,
the top 256 pages of memory behave like the other
pages of memory.
5/37
5 Page 
Figure 7. M25PE10 Block Diagram
Reset
TSL
S
C
D
Q
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
1FF00h
256 Byte
Data Buffer
FFFFh
M25PE10, M25PE20
Status
Register
1FFFFh
Top 256 Pages can
be made read-only
00000h
256 Bytes (Page Size)
X Decoder
000FFh
AI10814
11/37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M25PE20.PDF ] | |
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