PDF K7P161866A Data sheet ( Hoja de datos )

Número de pieza	K7P161866A
Descripción	(K7P161866A / K7P163866A) 512Kx36 AND 1Mx18 Synchronous Pipelined SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! www.DataSheet4U.com K7P163666A K7P161866A Document Title 512Kx36 & 1Mx18 Synchronous Pipelined SRAM 512Kx36 & 1Mx18 SRAM Revision History Rev. No. Rev. 0.0 History - Initial Document Rev. 0.1 - Absolute maximum ratings are changed VDD : 2.815 - > 3.13 VDDQ : 2.815 - > 2.4 VTERM : 2.815 - > VDDQ+0.5 (2.4V MAX) - Recommended DC operating conditions are changed VREF / VCM-CLK : 0.68 - > 0.6, 0.95 - > 0.9 - DC characteristics is changed ISBZZ : 150 - > 128 - AC Characteristics are changed TAVKH / TDVKH / TWVKH / TSVKH : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3 TKHAX / TKHDX / TKHWX / TKHSX : 0.5 / 0.5 / 0.5 - > 0.5 / 0.6 / 0.6 Rev. 0.2 - Recommended DC operating condition is changed Max VDIF-CLK : VDDQ+0.3 -> VDDQ+0.6 Rev. 0.3 - Correct typo VDD -> VDDQ: in MODE CONTROL at page4 Draft Date Dec. 2001 Oct. 2002 Remark Advance Advance Jan. 2003 Sep. 2003 Advance Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters. -1- Sep. 2003 Rev 0.3 1 page K7P163666A K7P161866A 512Kx36 & 1Mx18 SRAM FUNCTION DESCRIPTION The K7P163666A and K7P161866A are 18,874,368 bit Dual Mode (supports both Register Register and Late Select Mode) SRAM devices. They are organized as 524,288 words by 36 bits for K7P163666A and 1,048,576 words by 18 bits for K7P161866A, fabri- cated using Samsung's advanced CMOS technology. Late Write/Pipelined Read(RR) for x36/x18 organizations and Late Write/Late Select Read(LS) for x36 organization are supported. The chip is operated with a single +2.5V power supply and is compatible wtih HSTL input and output. The package is 119(7x17) Plastic Ball Grid Array with balls on a 1.27mm pitch. Read Operation for Register Register Mode(x36 and x18) During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock. Read Operation for Late Select Mode(x36) During read operations, addresses(SA) and controls except the Way Select Address(SAS) are registered during the first rising edge of K clock. The internal array(x72 bit data) is read between the first edge and the second edge, and as the Way Select Address(SAS) is registered at the second clock edge, x36 bit data is mux selected before the output register. Write Operation(Late Write) During write operations, addresses including the Way Select Address(SAS) and controls are registered at the first rising edge of K clock and data inputs are registered at the following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the timing of SW[a:d] is the same as the SW signal. Bypass Read Operation Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the SRAM array. Programmable Impedance Output Buffer Operation This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu- ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations. Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura- tion by connecting ZQ to VSS or VDD. Mode Control There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDD. These mode pins must be set at power-up and must not change during device operation. Power-Up/Power-Down Supply Voltage Sequencing The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down. Sleep Mode Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated. Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time. -5- Sep. 2003 Rev 0.3 5 Page K7P163666A K7P161866A 512Kx36 & 1Mx18 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control- ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram M1 TDI TMS TCK SRAM CORE BYPASS Reg. Identification Reg. Instruction Reg. Control Signals TAP Controller M2 TDO JTAG Instruction Coding IR2 IR1 IR0 Instruction TDO Output Notes 0 0 0 SAMPLE-Z Boundary Scan Register 1 0 0 1 IDCODE Identification Register 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 BYPASS Bypass Register 3 1 0 0 SAMPLE Boundary Scan Register 4 1 0 1 BYPASS Bypass Register 3 1 1 0 BYPASS Bypass Register 3 1 1 1 BYPASS Bypass Register 3 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction does not places DQs in Hi-Z. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 1 1 Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 Pause DR 1 Exit2 DR 1 Update DR 0 1 1 0 1 0 0 Select IR 0 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 1 0 0 0 0 - 11 Sep. 2003 Rev 0.3 11 Page

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