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PDF LH79525 Data sheet ( Hoja de datos )
| Número de pieza | LH79525 | |
| Descripción | System-on-Chip | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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Data Sheet
LH79524/LH79525 (A.1)
System-on-Chip
FEATURES
• Highly Integrated System-on-Chip
• High Performance: 76.205 MHz CPU Speed,
50.803 MHz maximum AHB clock (HCLK)
• 32-bit ARM720T™ RISC Core
– LH79524: 32-bit External Data Bus
– 208 CABGA package
– LH79525: 16-bit External Data Bus
– 176 LQFP package
• 8KB Cache with Write Back Buffer
• MMU (Windows CE™ Enabled)
• 16KB On-Chip SRAM
• Flexible, Programmable Memory Interface
– SDRAM Interface
– 512 MB External Address Space
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
– SRAM/Flash/ROM Interface
– 15-bit External Address Bus
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
• Multi-stream DMA Controller
– Four 32-bit Burst-Based Data Streams
• Clock and Power Management
– 32.768 kHz Oscillator for Real Time Clock
– 10 - 20 MHz Oscillator and On-chip PLL
– Active, Standby, Sleep, Stop1, and Stop2 Modes
– Externally-supplied Clock Options
• On-Chip Boot ROM
– Allows Booting from 8-, 16-, or 32-bit Devices
– NAND Flash Boot
• Low Power Modes
– Active Mode: 85 mA (MAX.)
– Standby Mode: 50 mA (MAX.)
– Sleep Mode: 3.8 mA (TYP.)
– Stop Mode 1: 420 μA (TYP.)
– Stop Mode 2: 25 μA (TYP.)
• USB Device
– Compliant with USB 2.0 Specifications (Full Speed)
– Four Endpoints
• Ethernet MAC, with MII and MDIO Interfaces
– IEEE 802.3 Compliant
– 10 and 100 Mbit/s Operation
• Analog-to-Digital Converter/Brownout Detector
– 10-bit ADC
– Pen Sense Interrupt
– Integrated Touch Screen Controller (TSC)
• I2C Module
• Integrated Codec Interface Support Features (I2S)
• Watchdog Timer
• Vectored Interrupt Controller
– 16 Standard and 16 Vectored IRQ Interrupts
– Interrupts Individually Configurable as IRQ or FIQ
• Three UARTs
– 16-entry FIFOs for Rx and Tx
– IrDA SIR Support on all UARTs
• Three 16-bit Timers with PWM capability
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
• Programmable General Purpose I/O Signals
– LH79524: 108 available pins on 14 ports
– LH79525: 86 available pins on 12 ports
• Programmable Color LCD Controller
– 16 (LH79524) or 12 (LH79525) Bits-per-Pixel
– Up to 800 × 600 resolution
– STN, Color STN, HR-TFT, AD-TFT, TFT
– TFT: Supports 64 k (LH79524) or 4 k (LH79525)
Direct Colors or 256 Colors selected from a
Palette of 64 k Colors; 15 Shades of Gray
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mbit/s
– Compatible with Common Interface Schemes
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital Inputs (excludes oscillator pins)
– XTALIN and XTAL32IN pins are 1.8 V ± 10%
• On-Chip regulator allows single 3.3 V supply
DESCRIPTION
The LH79524/LH79525, powered by an ARM720T,
is a complete System-on-Chip with a high level of inte-
gration to satisfy a wide range of requirements and
applications. The SoC has a fully static design, power
management unit, and low voltage operation (1.8 V
Core, 3.3 V I/O). With the on-chip voltage regulator, a
single 3.3 V supply can be used as well. Robust periph-
erals and a low-power RISC core provide high perfor-
mance at a reasonable price.
Devices containing lead-free solder formulations have different reflow
temperatures than leaded-solder formulations. When using both
solder formulations on the same PC board, consider the effect of
different reflow temperatures on the overall PCB assembly process.
ARM720T is a trademark of Advanced RISC Machines, LTD.
Data Sheet for Rev. A.1 Silicon
Version 1.0
1
1 page  
System-on-Chip
LH79524/LH79525
CABGA
PIN
SIGNAL NAME
M3
PB7/INT1/UARTTX0/
UARTIRTX0
N7 PC0/A16
R6 PC1/A17
T5 PC2/A18
P6 PC3/A19
R5 PC4/A20
T4 PC5/A21
P5 PC6/A22/nFWE
R4 PC7/A23/nFRE
P15 PD0/D8
P14 PD1/D9
N13 PD2/D10
T15 PD3/D11
N12 PD4/D12
T14 PD5/D13
P12 PD6/D14
T13 PD7/D15
B12
PE0/LCDLP/
LCDHRLP
D11 PE1/LCDDCLK
B13 PE2/LCDPS
C13 PE3/LCDCLS
D12
PE4/LCDDSPLEN/
LCDREV
B16 PE5/LCDVDDEN
B15
PE6/LCDVEEN/
LCDMOD
D14 PE7/nWAIT/nDEOT
A8 PF0/LCDVD6
A9 PF1/LCDVD7
B9 PF2/LCDVD8
C9 PF3/LCDVD9
B10 PF4/LCDVD10
A11 PF5/LCDVD11
B11 PF6/LCDEN/LCDSPL
A12 PF7/LCDFP/LCDSPS
A5 PG0/ETHERTXEN
B6 PG1/ETHERTXCLK
A6 PG2/LCDVD0
C7 PG3/LCDVD1
B7 PG4/LCDVD2
Table 1. LH79524 Pin Descriptions (Cont’d)
TYPE
DESCRIPTION
I/O
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit-
ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
I/O General Purpose I/O Signal — Port C0; multiplexed with Address A16
I/O General Purpose I/O Signal — Port C1; multiplexed with Address A17
I/O General Purpose I/O Signal — Port C2; multiplexed with Address A18
I/O General Purpose I/O Signal — Port C3; multiplexed with Address A19
I/O General Purpose I/O Signal — Port C4; multiplexed with Address A20
I/O General Purpose I/O Signal — Port C5; multiplexed with Address A21
I/O
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
I/O
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
I/O General Purpose I/O Signal — Port D0; multiplexed with Data D8
I/O General Purpose I/O Signal — Port D1; multiplexed with Data D9
I/O General Purpose I/O Signal — Port D2; multiplexed with Data D10
I/O General Purpose I/O Signal — Port D3; multiplexed with Data D11
I/O General Purpose I/O Signal — Port D4; multiplexed with Data D12
I/O General Purpose I/O Signal — Port D5; multiplexed with Data D13
I/O General Purpose I/O Signal — Port D6; multiplexed with Data D14
I/O General Purpose I/O Signal — Port D7; multiplexed with Data D15
I/O
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
I/O General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
I/O General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
I/O General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
I/O
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
I/O General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
I/O
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
I/O
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of
Transfer
I/O General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
I/O General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
I/O General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
I/O General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
I/O General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
I/O General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
I/O General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
I/O
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver
Counter reset
I/O General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable
I/O General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock
I/O General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
I/O General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
I/O General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
Data Sheet for Rev. A.1 Silicon
Version 1.0
5
5 Page 
System-on-Chip
LH79524/LH79525
PIN NO. SIGNAL NAME
80 A0
79 A1
78 A2
77 A3
76 A4
74 A5
73 A6
72 A7
71 A8
70 A9
69 A10
67 A11
65 A12
63 A13
62 A14
61 A15
99 D0
98 D1
97 D2
96 D3
95 D4
94 D5
93 D6
91 D7
117 SDCLK
116 SDCKE
119 DQM0
118 DQM1
115 nDCS0
114 nDCS1
113 nRAS
112 nCAS
104 nCS0/PM0
103 nCS1/PM1
102 nCS2/PM2
100 nCS3/PM3
110 nBLE0/PM4
109 nBLE1/PM5
106 nOE
111 nWE
130 USBDN
131 USBDP
11 AN0/UL/X+
14 AN1/UR/X–
17 AN2/LL/Y+/PJ3
Table 4. LH79525 Pin Descriptions
TYPE
DESCRIPTION
O External Address Bus
I/O External Data Bus
O SDRAM Clock
O SDRAM Clock Enable
O Data Mask Output to SDRAMs
O SDRAM Chip Select
O SDRAM Chip Select
O Row Address Strobe
O Column Address Strobe
O Static Memory Chip Select; multiplexed with GPO Port M[3:0]
O
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[5:4]
O Static Memory Output Enable
O Static Memory Write Enable
I/O USB Data Negative (Differential Pair output, single ended and Differential input)
I/O USB Data Positive (Differential Pair output, single ended and Differential input)
I ADC Input 0, 4 wire touch screen Upper Left, 5 wire touch screen X+
I ADC Input 1, 4 wire touch screen Upper Right, 5 wire touch screen X–
I
ADC Input 2, 4 wire touch screen Lower Left, 5 wire touch screen Y+; multiplexed with
GPIO Port J3 (input only)
Data Sheet for Rev. A.1 Silicon
Version 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH79525.PDF ] | |
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