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Xilinx - (XC3Sxx00E) Spartan-3E FPGA Family

Numéro de référence XC3S250E
Description (XC3Sxx00E) Spartan-3E FPGA Family
Fabricant Xilinx 
Logo Xilinx 





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XC3S250E fiche technique
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R Spartan-3E FPGA Family:
Complete Data Sheet
DS312 March 21, 2005
00
Module 1:
Introduction and Ordering Information
DS312-1 (v1.1) March 21, 2005
6 pages
• Introduction
• Features
• Architectural Overview
• Package Marking
Ordering Information
Module 2:
Functional Description
DS312-2 (v1.1) March 21, 2005
96 pages
• Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
Configuration
• Powering Spartan-3E FPGAs
Module 3:
DC and Switching Characteristics
DS312-3 (v1.0) March 1, 2005
18 pages
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- DCM Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v1.1) March 21, 2005
72 pages
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
IMPORTANT NOTE: The Spartan-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 March 21, 2005
www.xilinx.com
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