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PDF HMA510 Data sheet ( Hoja de datos )
| Número de pieza | HMA510 | |
| Descripción | 16 x 16-Bit CMOS Parallel Multiplier Accumulator | |
| Fabricantes | Intersil Corporation | |
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HMA510
April 1997
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Features
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (45ns) Multiply Accumulate Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1.0MHz
• HMA510 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• TTL Compatible Inputs/Outputs
• Three-State Outputs
Ordering Information
PART NUMBER
HMA510JC-45
HMA510JC-55
HMA510GC-55
TEMP. RANGE
(oC)
0 to 70
0 to 70
0 to 70
PACKAGE
68 Ld PLCC
68 Ld PLCC
68 Ld CPGA
PKG.
NO.
N68.95
N68.95
G68.B
Description
The HMA510 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier accumulator capable of operating at 45ns
clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Block Diagram
X0-15
16
RND SUB Y0-15 P0-15
TC ACC
16
PRELOAD
CLKP
REGISTER
REGISTER
REGISTER
CLKY
CLKX
XTP REGISTER
MULTIPLIER ARRAY
35
ACCUMULATOR
MSP REGISTER LSP REGISTER
3 16
35
16
OEX
OEM
OEL
P32-34
P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
1
File Number 2806.2
1 page  
HMA510
Input Formats
X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
(SIGN)
Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
(SIGN)
FIGURE 1. FRACTIONAL TWO’s COMPLEMENT INPUT
X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-15 2-14 2-13 2-12 2-11 2-10 2-9 2-8 2-7 2-6 2-5 2-4 2-3 2-2 2-1 -20
(SIGN)
Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-15 2-14 2-13 2-12 2-11 2-10 2-9 2-8 2-7 2-6 2-5 2-4 2-3 2-2 2-1 -20
(SIGN)
FIGURE 2. INTEGER TWO’S COMPLEMENT INPUT
X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-11 2-12 2-13 2-14 2-15 2-16
Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-11 2-12 2-13 2-14 2-15 2-16
FIGURE 3. UNSIGNED FRACTIONAL INPUT
X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
FIGURE 4. UNSIGNED INTEGER INPUT
Output Formats
XTP
34 33 32
-24 23 22
(SIGN)
MSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14
LSP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-15 2-14 2-13 2-12 2-11 2-10 2-9 2-8 2-7 2-6 2-5 2-4 2-3 2-2 2-1 -20
FIGURE 5. TWO’S COMPLEMENT FRACTIONAL OUTPUT
XTP
34 33 32
-234 233 232
(SIGN)
MSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
LSP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
FIGURE 6. TWO’S COMPLEMENT INTEGER OUTPUT
XTP
34 33 32
22 21 20
MSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
2-12-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-11 2-12 2-13 2-14 2-15 2-16
LSP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-17 2-18 2-19 2-20 2-21 2-222-232-242-252-262-272-282-292-302-31-232
FIGURE 7. UNSIGNED FRACTIONAL OUTPUT
3-5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HMA510.PDF ] | |
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