PDF AD9784 Data sheet ( Hoja de datos )

Número de pieza	AD9784
Descripción	TxDAC
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com 14-Bit, 200 MSPS/500 MSPS TxDAC+® with 2×/4×/8× Interpolation and Signal Processing Preliminary Technical Data AD9784 FEATURES 14-bit resolution, 200 MSPS input data rate Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes Single or dual-channel signal processing Selectable image rejection Hilbert transform Flexible calibration engine Direct IF transmission features Serial control interface Versatile clock and data interface SFDR: 90 dBc @10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.75 LSB INL = ±1.5 LSB 3.3 V compatible digital Interface On-chip 1.2 V reference 80-lead thermally enhanced TQFP package APPLICATIONS Digital quadrature modulation architectures Multicarrier WCDMA, GSM, TDMA, DCS, PCS, CDMA Systems PRODUCT DESCRIPTION The AD9784 is a 14-bit, high speed, CMOS DAC with 2×/4×/8× interpolation and signal processing features tuned for com- munications applications. It offers state of the art distortion and noise performance. The AD9784 was developed to meet the demanding performance requirements of multicarrier and third generation base stations. The selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains. The modulation modes allow convenient bandwidth placement and selectable sideband suppression. The flexible clock interface accepts a variety of input types such as 1 V p-p sine wave, CMOS, and LVPECL in single ended or differential mode. Internal dividers generate the required data rate interface clocks. The AD9784 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from 10 mA to 20 mA. The AD9784 is manufactured on an advanced low cost 0.25 µm CMOS process. P1B[15:0] P2B[15:0] DATACLK/ PLL_LOCK FUNCTIONAL BLOCK DIAGRAM LATCH ×1 LATCH 2× 2× 2× I fDAC/2 fDAC/4 fDAC/8 0 90 2× ×2 2× ×4 2× ×8 Q 0 90 0 90 ∆t ZERO STUFF 16-BIT DAC HILBERT FSADJ REFIO IOUTA IOUTB SDIO SDO CSB SCLK RESET CLK+ CLK– LPF CLOCK DISTRIBUTION AND CONTROL Figure 1. Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 1 page Preliminary Technical Data AD9784 DYNAMIC SPECIFICATIONS Table 2. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 Ω Doubly Terminated, unless otherwise noted Parameter Min Typ Max DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) 500 Output Settling Time (tST) (to 0.025%) Output Propogation Delay5 (tPD) Output Rise Time (10%–90%)6 Output Fall Time (90%–10%)6 Output Noise (IOUTFS = 20 mA) AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 160 MSPS; fOUT= 1 MHz 95 fDATA = MSPS; fOUT = MHz fDATA = MSPS; fOUT = MHz fDATA = MSPS; fOUT = MHz fDATA = MSPS; fOUT = MHz fDATA = MSPS; fOUT = MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS) fDATA = 160 MSPS; fOUT1 = 25 MHz; fOUT2 = 31 MHz 80 fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz Total Harmonic Distortion (THD) fDATA = MSPS; fOUT = MHz; 0 dBFS fDATA = MSPS; fOUT = MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fDATA = MSPS; fOUT = MHz; 0 dBFS fDATA = MSPS; fOUT = MHz; 0 dBFS Adjacent Channel Power Ratio (ACPR) WCDMA with MHz BW, MHz Channel Spacing IF = 16 MHz, fDATA = 65.536 MSPS IF = 32 MHz, fDATA = 131.072 MSPS Four-Tone Intermodulation MHz, MHz, MHz and MHz at –12 dBFS (fDATA = MSPS, Missing Center) AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = MHz MHz, MHz, MHz and MHz at dBFS fDATA = MSPS, fDAC = MHz Unit MSPS ns ns ns ns pA√Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dBFS dBFS dBc dBc dBFS dBFS 5 Propagation delay is delay from CLK input to DAC update. 6 Measured single-ended into 50 Ω load. Rev. PrC \| Page 5 of 52 5 Page Preliminary Technical Data Adjacent Channel Power Ratio (or ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Modulation The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = ejwt = coswt + jsinwt) and realizing real and imaginary components on the modulator output. AD9784 Complex Image Rejection In a traditional two part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. PrC \| Page 11 of 52 11 Page

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