PDF AD8376 Data sheet ( Hoja de datos )

Número de pieza	AD8376
Descripción	Ultra Low Distortion IF Dual VGA
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet FEATURES Dual independent digitally controlled VGAs Bandwidth of 700 MHz (−3 dB) Gain range: −4 dB to +20 dB Step size: 1 dB ± 0.2 dB Differential input and output Noise figure: 8.7 dB @ maximum gain Output IP3 of ~50 dBm at 200 MHz Output P1dB of 20 dBm at 200 MHz Dual parallel 5-bit control interface Provides constant SFDR vs. gain Power-down control Single 5 V supply operation 32-lead, 5 mm x 5 mm LFCSP APPLICATIONS Differential ADC drivers Main and diversity IF sampling receivers Wideband multichannel receivers Instrumentation GENERAL DESCRIPTION The AD8376 is a dual channel, digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high IP3, and low noise figure. The excellent distortion perform- ance and high signal bandwidth make the AD8376 an excellent gain control device for a variety of receiver applications. Using an advanced high speed SiGe process and incorporating proprietary distortion cancellation techniques, the AD8376 achieves 50 dBm output IP3 at 200 MHz. The AD8376 provides a broad 24 dB gain range with 1 dB resolution. The gain of each channel is adjusted through dedicated 5-pin control interfaces and can be driven using standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading impedance. Thus, the signal voltage gain is directly proportional to the load. Each channel of the AD8376 can be individually powered on by applying the appropriate logic level to the ENBA and ENBB power enable pins. The quiescent current of the AD8376 is typically 130 mA per channel. When powered down, the Ultralow Distortion IF Dual VGA AD8376 FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 VCCA GNDA IPA+ IPA– VCMA VCMB IPB+ IPB– CHANNEL A GAIN DECODER α α CHANNEL B GAIN DECODER AD8376 POST-AMP POST-AMP OPA+ OPA+ OPA– OPA– ENBA ENBB OPB+ OPB+ OPB– OPB– B4 B3 B2 B1 B0 VCCB Figure 1. GNDB AD8376 consumes less than 5 mA and offers excellent input-to- output isolation, lower than −50 dB at 200 MHz. Fabricated on an Analog Devices, Inc., high speed SiGe process, the AD8376 is supplied in a compact, thermally enhanced, 5 mm × 5mm 32-lead LFCSP package and operates over the temperature range of −40°C to +85°C. –40 65 –50 60 –60 55 OIP3 –70 50 –80 –90 –100 45 HD2 40 HD3 35 –110 40 60 30 80 100 120 140 160 180 200 FREQUENCY (MHz) Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD8376 Data Sheet Parameter POWER INTERFACE Supply Voltage VCC and Output Quiescent Current with Both Channels Enabled vs. Temperature Power-Down Current, Both Channels vs. Temperature POWER-UP/GAIN CONTROL VIH VIL Logic Input Bias Current Conditions Thermal connection made to exposed paddle under device −40°C ≤ TA ≤ +85°C ENBA and ENBB Low −40°C ≤ TA ≤ +85°C Pin A0 to Pin A4, Pin B0 to Pin B4, Pin ENBA, and Pin ENBB Minimum voltage for a logic high Maximum voltage for a logic low Min 4.5 245 1.6 Typ 5.0 250 5.4 900 Max Unit 5.5 V 255 mA 285 mA mA 7 mA V 0.8 V nA Table 2. Gain Code vs. Voltage Gain Look-Up Table 5-Bit Binary Gain Code Voltage Gain (dB) 00000 +20 00001 +19 00010 +18 00011 +17 00100 +16 00101 +15 00110 +14 00111 +13 01000 +12 01001 +11 01010 +10 01011 +9 01100 +8 5-Bit Binary Gain Code 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 >11000 Voltage Gain (dB) +7 +6 +5 +4 +3 +2 +1 0 −1 −2 −3 −4 −4 Rev. B \| Page 4 of 24 5 Page AD8376 2 1 CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt A CH1 960mV Figure 22. Gain Step Time Domain Response 2 1 CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt A CH1 960mV Figure 23. ENBL Time Domain Response REF1 POSITION –420mV/DIV REF1 SCALE 0pF 2V 10pF EACH SIDE INPUT RRR143 REF 1 2.0V 2.5ns M2.5ns 20.0GS/s IT 10.0ps/pt A CH4 28.0mV Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Data Sheet REF3 POSITION –600mV/DIV REF3 SCALE 0pF 500mV 10pF EACH SIDE INPUT RR13 REF3 500mV 2.5ns M2.5ns 20.0GS/s IT 10.0ps/pt A CH4 28.0mV Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB 2 REF1 OUTPUT INPUT REF1 POSITION –1.08/DIV REF1 SCALE 50mV RISE (C2) 1.339ns FALL(C2) 1.367ns CH2 500mV M2.5ns 20Gsps REF1 50.0mV IT 2.5ps/pt A CH2 Figure 26. Large Signal Pulse Response –590mV 0 –5 –10 –15 –20 –25 –30 10 100 FREQUENCY (MHz) Figure 27. S11 vs. Frequency 180 120 60 0 –60 –120 –180 1000 Rev. B \| Page 10 of 24 11 Page

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