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PDF ZL50130 Data sheet ( Hoja de datos )
| Número de pieza | ZL50130 | |
| Descripción | Ethernet Pseudo-Wires across a PSN | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL50130
Ethernet Pseudo-Wires across a PSN
Data Sheet
Applications
• Ethernet Pseudo-Wires across a Packet Switch
Network
Features
Ethernet Pseudo-Wire Emulation Functions
Supports the following functions for Ethernet Pseudo-
Wire emulation over the packet domain:
• Transports the complete Ethernet frame (less
preamble and FCS) across the PSN
• Supports up to 127 point-to-point pseudo-wire
links across the PSN
• VLAN priority field may be used to determine
class of service on the PSN
• complies with the standards for Ethernet pseudo-
wires proposed in the IETF’s PWE3 working
group
Network Interfaces
• 3 x 100 Mbit/s MII interfaces
October 2004
Ordering Information
ZL50130 PBGA
-40°C to +85°C
System Interfaces
• Flexible 32-bit host CPU interface (Motorola
PowerQUICC™ II compatible)
• Dual address DMA transfer of packets to or from
the CPU
• On-chip packet memory for self-contained
operation
Packet Processing Functions
• Flexible, multi-protocol packet encapsulation, with
support for IPv4/6, MPLS, L2TP, PWE3
• Wire speed processing and forwarding of packets
• Packet sequencing and re-ordering where
required
• Four classes of service with programmable
priority mechanisms (WFQ and SP)
• Flexible classification of incoming packets at
layers 2, 3, 4 and 5
Host Processor Interface
Motorola PowerQUICCTM II compatible
MAC
Host Processor Interface
with DMA support
packet
receive/classifier
protocol
engine
task
manager
packet transmit
- add layer 2/3 headers
memory management /
on-chip packet memory
MAC
Optional Off-chip Packet Memory
0-8 MBytes SSRAM
Figure 1 - High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50130
Data Sheet
List of Figures
Figure 1 - High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Provider Edge Inter-working Function using the ZL50130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - ZL50130 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 - ZL50130 Data Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 - ZL50130 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6 - Task Manager Routing Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 8 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 9 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 10 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11 - External RAM Read and Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 12 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 15 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 17 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18 - Powering Up the ZL50130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5
Zarlink Semiconductor Inc.
5 Page 
Ball Signal Assignment
Ball
Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
B2
B3
B4
B5
B6
B7
Signal Name
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
ZL50130
Ball
Number
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
Signal Name
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
11
Zarlink Semiconductor Inc.
Data Sheet
Ball
Number
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
Signal Name
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DATA[3]
RAM_DATA[1]
N/C
RAM_DATA[0]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL50130.PDF ] | |
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