|
|
PDF ZL30102 Data sheet ( Hoja de datos )
| Número de pieza | ZL30102 | |
| Descripción | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ZL30102 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ZL30102
T1/E1 Stratum 4/4E Redundant System
Clock Synchronizer for DS1/E1 and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between an H.110 primary
master clock and a secondary master clock
• Supports Telcordia GR-1244-CORE Stratum 4 and
4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s
and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
• Simple hardware control interface
• Manual and Automatic hitless reference switching
between any combination of valid input reference
frequencies
• Accepts three input references and synchronizes
to any combination of 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz
and either 4.096 MHz and 8.192 MHz or
32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1x10-7
November 2005
Ordering Information
ZL30102QDG 64 pin TQFP Trays, Bake & Drypack
ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
• Provides Lock, Holdover and selectable Out of
Range indication
• Attenuates wander from 1.8 Hz
• Less than 0.6 nspp intrinsic jitter on all output
clocks
• External master clock source: Clock Oscillator or
Crystal
Applications
• Synchronization and timing control for multi-trunk
DS1/ E1 terminal systems such as DSLAMs,
Gateways and PBXs
• Clock and frame pulse source for H.110 CT Bus,
ST-BUS, GCI and other time division multiplex
(TDM) buses
REF0
REF1
REF2
REF2_SYNC
REF_FAIL0
REF_FAIL1
REF_FAIL2
OOR_SEL
REF_SEL1:0
RST
OSCi OSCo TIE_CLR
FASTLOCK LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
DS2
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C6o
TRST
MODE_SEL1:0 SEC_MSTR HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL30102
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - DS1 Out-of-Range Thresholds for OOR_SEL=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - E1 Out-of-Range Thresholds for OOR_SEL=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - REF2_SYNC Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17 - Examples of REF2 & REF2_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18 - Clock Redundancy with Two Independent Timing Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22 - Typical Clocking Architecture of an ECTF H.110 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 28 - DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Zarlink Semiconductor Inc.
5 Page 
ZL30102
Data Sheet
Pin #
58
59
60
61
62
63
64
Name
Description
REF2_SYNC
REF2 Synchronization Frame Pulse (Input). This is the 8 kHz frame pulse
synchronization input associated with the REF2 reference. While the PLL is locked to the
REF2 input reference the output (multi) frame pulses are synchronized to this input. This
pin is internally pulled down to GND.
SEC_MSTR
Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary
Master mode of operation with 1.8 Hz DPLL loop filter bandwidth. A logic high selects
Secondary Master mode which forces the PLL to clear its TIE corrector circuit and lock to
the selected reference using a high bandwidth loop filter and a phase slope limiting of
9.5 ms/s.
OOR_SEL Out Of Range Selection (Input). This input selects the frequency out of range limits of
the reference inputs, see Table 1 on page 19.
VDD Positive Supply Voltage. +3.3 VDC nominal
NC No internal bonding Connection. Leave unconnected.
TIE_CLR
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
FASTLOCK Fast Lock (Input). Set temporarily high to allow the ZL30102 to quickly lock to the input
reference (one second locking time).
3.0 Functional Description
The ZL30102 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization
signals to interface circuits for the following types of primary rate digital transmission links, see Table 1:
• DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
• E1 compliant with ITU-T G.703 and ETSI ETS 300 011
Figure 1 is a functional block diagram of the ZL30102 which is described in the following sections.
3.1 Reference Select Multiplexer (MUX)
The ZL30102 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected
as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs.
The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 8 kHz frame pulse supplied to the REF2_SYNC input. This feature supports the implementation
of Primary and Secondary Master system clocks in H.110 systems.
3.2 Reference Monitor
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL30102.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ZL30100 | T1/E1 System Synchronizer |  Zarlink Semiconductor Inc |
| ZL30101 | T1/E1 Stratum 3 System Synchronizer | Zarlink Semiconductor Inc |
| ZL30102 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer | Zarlink Semiconductor |
| ZL30105 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer | Zarlink Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |