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PDF MAS9186 Data sheet ( Hoja de datos )
| Número de pieza | MAS9186 | |
| Descripción | 8 X 8-bit D to A Converter 3-pin Serial Data Interface Low Voltage Output Buffer | |
| Fabricantes | Micro Analog systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAS9186 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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This is preliminary information on a new
product under development. Micro Analog
Systems Oy reserves the right to make any
changes without notice.
DA9186.001
29 January, 2004
MAS9186
8 X 8-bit D to A Converter
• 3-pin Serial Data Interface
• Low Voltage Output Buffer
DESCRIPTION
MAS9186 is 8-channel 8-bit DAC, designed
primarily for trimmer replacement. Device is
controlled by a simple 3-line input. The output
buffers operate in the entire voltage range from
ground to the positive power supply rail.
FEATURES
• Eight 8-bit DACs on a single monolithic chip
• Voltage level output
• TSSOP 16 package
• Single +2.7V supply
• Power-on reset
BLOCK DIAGRAM
DAC is selected with three first bits in serial input
data (SDI-pin) and the DAC output value is set
according to the last 8 bits in serial input data.
APPLICATIONS
• High resolution monitors
• Automatic gain control
• Trimmer replacement
SDI
CLK
11-bit
Shift
Register
8-bit data
XCS
Address
Decoder
VREFH VREFL
VDD
(XRESET in
MAS9186A1)
GND
MAS9186A2
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O8
O7
O6
O5
O4
O3
O2
O1
1 (9)
1 page  
DA9186.001
29 January, 2004
OPERATING MODES
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)
(note: VREFL=GND in case of MAS9186A1). XRESET pin is used for middle code preset: DAC registers are
reset and middle code will appear at the DAC output.
Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.
Rising XCS-pin stops data reading and 11 CLK-cycles are used as the input data (3 address bits and 8 data
bits). The last 11 bits before rising XCS are used as input data.
◆ Timing diagram
SDI A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
XCS
DAC Register Load
VOUT
APPLICATION AND TEST CIRCUIT INFORMATION
Controller
+3.0v
Clock
Data In
Latch
100 nF
16
VDD
1
VREFH
MAS9186A2
8 XSHDN
12
CLK
13 SDI
9 XCS
GND
10
O8
O7
O6
O5
O4
O3
O2
O1
VREFL
11
15
14
7
6
5
4
3
2
5 (9)
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MAS9186.PDF ] | |
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