PDF K7Q161852A Data sheet ( Hoja de datos )

Número de pieza	K7Q161852A
Descripción	(K7Q161852A / K7Q163652A) 512Kx36 & 1Mx18 QDRTM b2 SRAM
Fabricantes	Samsung semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de K7Q161852A (archivo pdf) en la parte inferior de esta página. Total 17 Páginas
No Preview Available ! K7Q163652A K7Q161852A www.DataSheet4U.com 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Amendment 1) Page 3,4 PIN NAME DESCRIPTION W (4A) : from Read Control Pin to Write Control R (8A) : from Write Control Pin to Read Control BW0(7B),BW1(7A),BW2(5A),BW3(5B) : from Read Control Pin to Byte Wrtie Control 2) Page 7 STATE DIAGRAM from LEAD NOP to READ NOP 0.2 1. Amendment 1) Page 8 WRITE TRUTH TABLE(x36) BW2,BW3 values for WRITE ALL BYTEs( K↑ ) and WRITE ALLBYTEs( K↑ ) : from "H" to " L" 2) Page 13 TIMING WAVE FORMS Note 2 supplement 0.3 1. 1.8V I/O supply voltage addition 1) Page 2 FEATURES 2) Page 3,4 PIN NAME VDDQ 3) Page 10, OPERATING CONTITIONS 4) Page 11 AC TEST CONTITIONS 2. Amendment 1) Page 15 BOUNDARY SCAN ORDER EXIT 0.4 1. Icc, Isb addition 2. 1.8V Vddq addition 0.5 1. Reserved pin for high density name change from NC to Vss/SA 1.0 1. Final SPEC release 2. Modify thermal resistance Draft Date April, 30, 2001 May, 13, 2001 Remark Advance Advance May, 26, 2001 Advance June, 11, 2001 Advance Sep,03, 2001 Nov, 30, 2001 July, 03. 2002 Advance Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. - 1 - July 2002 Rev 1.0 1 page K7Q163652A K7Q161852A 512Kx36 & 1Mx18 QDRTM b2 SRAM GENERAL DESCRIPTION The K7Q163652A and K7Q161852A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7Q163652A and 1,048,576 words by 18 bits for K7Q161852A. The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K, and transfered out of sram on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn around. Address, data inputs, and all control signals are synchronized to the input clock ( K or K ). Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high, the data outputs are synchronized to the input clocks ( K and K ). Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fiexd to 2-bit sequential for both read and write operations. Synchronous pipeline read and early write enable high speed operations. Simple depth expansion is accomplished by using R and W for port selection. Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system. The K7Q163652A and K7Q161852A are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce. Read Operations Read cycles are initiated by activating R at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command. The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge. Next burst data is triggered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the R is disabled after a read operation, the K7Q163652A and K7Q161852A will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state. - 5 - July 2002 Rev 1.0 5 Page K7Q163652A K7Q161852A 512Kx36 & 1Mx18 QDRTM b2 SRAM AC TEST CONDITIONS Parameter Symbol Value Unit Core Power Supply Voltage VDD 2.4~2.6 V Output Power Supply Voltage VDDQ 1.4~1.9 V Input High/Low Level VIH/VIL 1.25/0.25 V Input Reference Level VREF 0.75 V Input Rise/Fall Time TR/TF 0.3/0.3 ns Output Timing Reference Level VDDQ/2 V Note: Parameters are tested with RQ=250Ω AC TEST OUTPUT LOAD VREF 0.75V VDDQ/2 SRAM Zo=50Ω 50Ω 250Ω ZQ PIN CAPACITANCE PRMETER SYMBOL Address Control Input Capacitance CIN Input and Output Capacitance COUT Clock Capacitance CCLK Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V. 2. Periodically sampled and not 100% tested. TESTCONDITION VIN=0V VOUT=0V - MIN MAX Unit NOTES 4 5 pF 6 7 pF 5 6 pF THERMAL RESISTANCE PRMETER SYMBOL TYP Unit NOTES Junction to Ambient Junction to Case Junction to Pins θJA 24.0 °C/W θJC 2.8 °C/W θJB 5.5 °C/W Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x θJA APPLICATION INFORMATION 1Mx18 Data In Data Out Address R W BW0-7 MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK SRAM#1 R=250Ω Vt R ZQ D0-17 Q0-17 SA R W BW0 BW1 C C K K Vt Vt R=50Ω Vt=VREF SRAM#4 R=250Ω ZQ D0-17 Q0-17 SA RW BW0 BW1 C C K K Vt Vt R - 11 - July 2002 Rev 1.0 11 Page

Páginas	Total 17 Páginas
PDF Descargar	[ Datasheet K7Q161852A.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
K7Q161852A	(K7Q161852A / K7Q163652A) 512Kx36 & 1Mx18 QDRTM b2 SRAM	Samsung semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar