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PDF A49LF040 Data sheet ( Hoja de datos )
| Número de pieza | A49LF040 | |
| Descripción | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory | |
| Fabricantes | AMIC Technology | |
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Preliminary
A49LF040
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
Document Title
4 Mbit CMOS 3.3 Volt-only Low Pin Count Flash Memory
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Add Pb-Free package type
Issue Date
February 17, 2004
August 20, 2004
Remark
Preliminary
PRELIMINARY (August, 2004, Version 0.1)
AMIC Technology, Corp.
1 page  
A49LF040
Table 1: Pin Description
Symbol
Pin Name
Type
Interface
A/A
Mux
LPC
Descriptions
A10-A0
Address
IN X
Inputs for addresses during Read and Write operations in A/A Mux
mode. Row and column addresses are latched by R/C# pin.
I/O7-I/O0
Data
I/O X
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE# is high.
OE#
Output Enable
IN X
To control the data output buffers.
WE#
Write Enable
IN X
To control the Write operations.
MODE
Interface
Configuration Pin
IN
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, LPC mode is enabled.
X X This pin must be setup at power-up or before return from reset and
not change during device operation. This pin is internally pulled
down with a resistor between 20-100 KΩ.
INIT#
Initialize
IN
This is the second reset pin for in-system use. INIT# and RST#
X pins are internally combined and initialize a device reset when
driven low.
ID[3:0]
Identification Inputs IN
These four pins are part of the mechanism that allows multiple
LPC devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
X boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count strapping.
These pins are internally pulled down with a resistor between 20-
100 KΩ.
GPI[4:0]
General Purpose
Inputs
IN
These individual inputs can be used for additional board flexibility.
The state of these pins can be read immediately at boot, through
X
LPC internal registers. These inputs should be at their desired
state before the start of the PCI clock cycle during which the read
is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
TBL#
Top Block Lock
IN
To prevent any write operations to the Boot Block when driven low,
X
regardless of the state of the block lock registers. When TBL# is
high it disables hardware write protection for the top Boot Block.
This pin cannot be left unconnected.
LAD[3:0]
LPC I/Os
I/O
X I/O Communications in LPC mode.
LCLK
Clock
IN
X
To provide a clock input to the device. This pin is the same as that
for the PCI clock and adheres to the PCI specifications.
LFRAME#
Frame
IN
X
To indicate start of a data transfer operation; also used to abort an
LPC cycle in progress.
RST#
Reset
IN X X To reset the operation of the device
WP#
Write Protect
IN
When low, prevents any write operations to all but the highest
X addressable block. When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
R/C#
Row/Column Select IN
X
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
RB#
Ready/Busy#
OUT X
To determine if the device is busy in write operations. Valid only in
A/A Mux mode.
RES
Reserved
X Reserved. These pins must be left unconnected.
VDD
Power Supply
PWR X
X To provide power supply (3.0-3.6Volt).
VSS
Ground
PWR X X Circuit ground. All VSS pins must be grounded.
NC No Connection
X X Unconnected pins.
1. IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY (August, 2004, Version 0.1)
4
AMIC Technology, Corp.
5 Page 
A49LF040
JEDEC ID Registers
The JEDEC ID registers identify the device as A49LF040 and
manufacturer as SST in LPC mode. See Table 9 for memory
address locations for its respective JEDEC ID location.
Table 8: General Purpose Inputs Register
Bit Bit
Function
Pin Number
32-PLCC 32-TSOP
7:5 -
Reserved
-
-
4 GPI[4] GPI_REG Bit 4 30
6
3 GPI[3] GPI_REG Bit 3
3
11
2 GPI[2] GPI_REG Bit 2
4
12
1 GPI[1] GPI_REG Bit 1
5
13
0 GPI[0] GPI_REG Bit 0
6
14
Table 9 Memory Map Register Addresses for A49LF040
Device#
Hardware Strapping
ID[3:0]
GPI_REG
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FFBC 0100H
FFB4 0100H
FFAC 0100H
FFA4 0100H
FF9C 0100H
FF94 0100H
FF8C 0100H
FF84 0100H
FF3C 0100H
FF34 0100H
FF2C 0100H
FF24 0100H
FF1C 0100H
FF14 0100H
FF0C 0100H
FF04 0100H
Manufacturer
FFBC 0000H
FFB4 0000H
FFAC 0000H
FFA4 0000H
FF9C 0000H
FF94 0000H
FF8C 0000H
FF84 0000H
FF3C 0000H
FF34 0000H
FF2C 0000H
FF24 0000H
FF1C 0000H
FF14 0000H
FF0C 0000H
FF04 0000H
JEDEC ID
Continuation
FFBC 0003H
FFB4 0003H
FFAC 0003H
FFA4 0003H
FF9C 0003H
FF94 0003H
FF8C 0003H
FF84 0003H
FF3C 0003H
FF34 0003H
FF2C 0003H
FF24 0003H
FF1C 0003H
FF14 0003H
FF0C 0003H
FF04 0003H
Device
FFBC 0001H
FFB4 0001H
FFAC 0001H
FFA4 0001H
FF9C 0001H
FF94 0001H
FF8C 0001H
FF84 0001H
FF3C 0001H
FF34 0001H
FF2C 0001H
FF24 0001H
FF1C 0001H
FF14 0001H
FF0C 0001H
FF04 0001H
PRELIMINARY (August, 2004, Version 0.1)
10
AMIC Technology, Corp.
11 Page | ||
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| PDF Descargar | [ Datasheet A49LF040.PDF ] | |
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