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Descripción Functional Differences
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Freescale Semiconductor
Engineering Bulletin
EB632
Rev. 2, 1/2005
Functional Differences Between
MSC8101 (Mask 2K42A) and MSC8103
(Mask 2K87M)
1 Introduction
This document describes the differences between MSC8101
mask set 2K42A and MSC8103 mask set 2K87M. These
differences include:
• System Interface Unit (SIU) changes:
— Internal Memory Map Register (IMMR) MASKNUM
field value
— Addition of the Internal Memory Map Mirror Register
(IMMMR)
• Reset changes:
— Modes
— Hard Reset Configuration Word (HRCW) layout
• Boot source changes
• Clock changes
— Clock scheme
— System Clock Mode Register (SCMR)
— Addition of the CLKODIS field to the System Clock
Control Register (SCCR)
— Clock modes
CLKIN to CLKOUT delay change
— Maximum clock frequencies change
• Memory map addition of IMMMR
• ORx in UPM mode, bit 27 functionality difference
• Host interface (HDI16) changes
• Direct memory access (DMA) controller transfer code
(TC) definitions
CONTENTS
1 Introduction.........................................................1
2 Summary of Differences .....................................2
3 SIU ......................................................................3
4 Reset....................................................................6
5 Boot.....................................................................9
6 Clock System ....................................................14
7 Memory Map ....................................................22
8 ORx in UPM Mode...........................................22
9 HDI16 ...............................................................22
10 DMA Transfer Code Definitions ......................36
11 Interrupt System................................................36
12 Debugging.........................................................36
13 EFCOP ..............................................................37
14 CPM ..................................................................37
15 Errata.................................................................56
A Bootloader Program ..........................................82
© Freescale Semiconductor, Inc., 2002, 2005. All rights reserved.

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EB632 pdf
3.1.2 2K87M Mask Set IMMR Values
SIU
IMMR
Internal Memory Map Register
0x101A8
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Type
Reset
ISB
R/W
Depends on reset configuration sequence.
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Type
Reset
PARTNUM
MASKNUM
R
IMMR identifies a specific device as well as the base address for the internal memory map. Software can deduce
availability and location of any on-chip system resources from the values in IMMR. PARTNUM and MASKNUM
are mask programmed and cannot be changed for any particular device.
Table 3. IMMR Bit Descriptions
Bits
ISB
0–14
15
PARTNUM
16–23
MASKNUM
24–31
Description
Internal Space Base
Defines the base address of the internal memory space. The value of ISB is configured at
reset to one of seven addresses; the software can then change it to any value. The default
address is based on the ISB bits in the Hard Reset Configuration Word. The default is zero,
which maps to address 0xF0000000.
ISB defines the 15 msbs of the memory map register base address. IMMR itself is mapped
into the internal memory space region. As soon as the ISB is written with a new base
address, the IMMR base address is relocated according to the ISB. ISB enables the
configuration of multiple-MSC8103 systems.
Reserved. Write to zero for future compatibility.
Part Number
This field is mask-programmed with a code corresponding to the part number of the part on
which the SIU is located. It helps factory test and user code that is sensitive to part
changes. This field changes when the part number changes. For example, it would change
if any new module is added or if the size of any memory module changes. It does not
change if the part is changed to fix a bug in an existing module.
Mask Number
This field is mask-programmed with a code corresponding to the mask number of the part
on which the SIU is located. It helps factory test and user code that is sensitive to part
changes. It is programmed in a commonly changed layer and should be changed for all
mask set changes.
Settings
Implementation-dependent
The MSC8103 has an ID of
0x50.
The MSC8103 mask set
2K87M has an ID of 0x12.
3.2 Internal Memory Map Mirror Register (IMMMR)
The 2K87M mask set adds a new Internal Memory Map Mirror Register (IMMMR) which has a fixed address
controlled by the QBus Bank 1 (0x00F8FFC0) and the same register fields as the IMMR. It reflects the contents of
the IMMR. If the ISB in the IMMR is modified, the base address of all SIU and CPM registers, including the
IMMR, changes to the new value selected by the ISB. In such a case, the device or external masters may not be able
to access the registers. Since the IMMMR does not reside in the same base memory area, it is always available at its
fixed address. You can read the current ISB value from the IMMMR and determine the current internal base
address from that value.
Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
Freescale Semiconductor
5

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EB632 arduino
Boot
Bit
Description
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CSE1
Block Size
Notes: 1. CSE = checksum enable. Set this bit when a checksum comparison is needed.
2. Since the EPROMS that support the I2C protocol are small, 15 bits are sufficient to define the block size.
Figure 2. Checksum Enable Bit + Block Size
In addition, the following rules apply:
• The source data must be in big-endian format, with the most significant part at the lower-order address.
• To enable checksum, set the CSE bit. To disable checksum, clear the CSE bit.
• Block size includes the checksum and checksum.
• Each address must be aligned on a 16-byte boundary.
• Maximum size for a block is 64 KB.
• Checksum is performed on all block words, including addresses and sizes.
• The block size should be a multiple of 32 bits.
• If the next block address is 0x0, the bootloader treats the next block as sequential.
• All addresses should be located in SRAM. The address should be given as a DSP internal address.
The end of the boot code stream is indicated by a special boot end block with the structure shown in Table 9.
Table 9. Structure of the Boot End Block
Word
1
2
3
4
5
6
7
8
0x0000
0x0000
Boot start address, most significant part
Boot start address, least significant part
0x0000
0x0000
Checksum—xor
Checksum—xor
Description
The first two words indicate the end of the source blocks. At least one block of source code must be loaded when
the bootloader is invoked. The boot start address indicates the address at which the boot program execution starts.
This address must be aligned on a 16-byte boundary. The bootloader routine expects at least one code block in
addition to the boot end block. The sequence is repeated for subsequent blocks, until the final block in the data
stream is reached.
5.6 Load Procedure
The bootloader program uses the I2C serial interface to access data in the EPROM and to program the I2C
parameter RAM and registers. The I2C uses BDs and buffers to read and write data. The bootloader prepares and
keeps track of the BDs and buffers for program loading.
To enable multi-master support, the first 14 bytes of the EPROM are reserved for an address table, which is also
accessed in single-master mode. The table entries contain the location of the boot code.The loading process starts
by calculating the entry address and reading the boot code location address. Then the code loading starts by reading
the first 4 block words from the EPROM. The size of block, where to load it, the location of the next block in
EPROM, and checksum enable are extracted.
Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
Freescale Semiconductor
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