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PDF AD8112 Data sheet ( Hoja de datos )
| Número de pieza | AD8112 | |
| Descripción | fully buffered crosspoint switch matrix that operates | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Low cost, 16 × 8, high speed, nonblocking switch array
Pin-compatible 16 × 16 version available (AD8113)
Serial or parallel programming of switch array
Serial data out allows daisy chaining control of multiple
16 × 8 arrays to create larger switch arrays
Output disable allows connection of multiple devices
without loading the output bus
Complete solution
Buffered inputs
8 output amplifiers
Operates on ±5 V or ±12 V supplies
Low supply current of 54 mA
Excellent audio performance VS = ±12 V
±10 V output swing
0.002% THD at 20 kHz maximum 20 V p-p (RL = 600 Ω)
Excellent video performance VS = ±5 V
0.1 dB gain flatness of 10 MHz
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Excellent ac performance
−3 dB bandwidth 60 MHz
Low all-hostile crosstalk of −83 dB at 20 kHz
Reset pin allows disabling of all outputs (connected to a
capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance/DVR
Analog/digital audio routers
Video routers (NTSC, PAL, S-Video, SECAM)
Multimedia systems
Video conferencing
GENERAL DESCRIPTION
The AD8112 is a low cost, fully buffered crosspoint switch matrix
that operates on ±12 V for audio applications and ±5 V for
video applications. It offers a −3 dB signal bandwidth greater
than 60 MHz and channel switch times of less than 60 ns with
0.1% settling for use in both analog and digital audio. The
AD8112 operated at 20 kHz has a crosstalk performance of
−83 dB and isolation of 90 dB. In addition, ground/power pins
surround all inputs and outputs to provide extra shielding for
operation in the most demanding audio routing applications.
With a differential gain and differential phase better than 0.1%
and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,
the AD8112 is suitable for many video applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Audio/Video, 60 MHz, 16 × 8,
Gain of +2 Crosspoint Switch
AD8112
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
40 40
PARALLEL LATCH
40
DECODE
8 × 5:16 DECODERS
NO
CONNECT
8
AD8112
OUTPUT
128 BUFFER
G = +2
A0
A1
A2
DATA
OUT
SWITCH
MATRIX
Figure 1.
The AD8112 includes eight independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs
so that off channel loading is minimized. The AD8112 has a gain
of +2. It operates on voltage supplies of ±5 V or ±12 V while
consuming only 34 mA or 31 mA of current, respectively. The
channel switching is performed via a serial digital control (which
can accommodate the daisy chaining of several devices) or via
a parallel control, allowing updating of an individual output
without reprogramming the entire array.
The AD8112 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
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AD8112
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
1
CLK
0
1
DATA IN
0
t2
t1 t3
OUT07 (D4)
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t7
Symbol
t1
t2
t3
t4
t5
t6
t7
Limit
Min Typ Max
20
100
20
100
0
50
200
50
16
100
200
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT07 (D3)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
Figure 2. Timing Diagram, Serial Mode
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
Table 3. Logic Levels
Pins
RESET, SER/PAR,
CLK, DATA IN, CE,
UPDATE
VIH
2.0 V min
DATA OUT
VIL
0.8 V max
VOH
2.7 V min
VOL
0.5 V max
IIH
20 μA max
IIL
−400 μA min
IOH
−400 μA max
IOL
3.0 mA min
Rev. 0 | Page 5 of 28
5 Page 
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I/O SCHEMATICS
VCC
ESD
INPUT
ESD
AVEE
Figure 7. Analog Input
VCC
ESD
ESD
OUTPUT
AVEE
Figure 8. Analog Output
VCC
ESD
RESET
ESD
20kΩ
DGND
Figure 9. Reset Input
AD8112
ESD
INPUT
ESD
VCC
DGND
Figure 10. Logic Input
VCC
2kΩ ESD
OUTPUT
ESD
DGND
Figure 11. Logic Output
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD8112.PDF ] | |
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