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PDF W83194BR-640 Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-640 | |
| Descripción | 166MHZ CLOCK | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83194BR-640
166MHZ CLOCK FOR SIS CHIPSET
W83194BR-640
Data Sheet Revision History
Pages
1 n.a.
2 n.a.
3
4
5
6
7
8
9
10
Dates Version
02/Apr
1.0
Version
On Web
n.a.
1.0
Main Contents
All of the versions before 0.50 are for internal use.
Change version and version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: April. 2001
- 1 - Revision 1.0
1 page  
W83194BR-640
REF1^/&FS1
24_48MHz#/
&AGPSEL
48MHz ^
PCI clocks.
3 I/O 3.3V, 14.318MHz reference clock output. Internal
120kΩ pull-down.This pin has 1.5X drive strength.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
23 I/O 24MHz or 48MHz selected by Register.
AGPSEL at initial power up for H/W selecting the
output frequency of AGP clocks. Internal 120KΩ pull-
down.
22 O 48MHz output for USB. This pin has 1.5X drive
strength.
4.5 Power Management Pins
SYMBOL
PIN
AGP_STOP#
SDRAM_STOP#
PD#
CPU_STOP#
PCI_STOP#
29
30
31
32
33
FUNCTION
AGP clock stop control pin.
SDRAM clock stop control pin.
Power Down pin, if PD#=0, all clocks are stopped.
CPU clock stop control pin.
PCI clock stop control pin.
4.6 Power Pins
SYMBOL
VddR
VddAPIC
Vdd
VddC
VddAGP
VddP
VddSD
Vdd48
Vss
PIN FUNCTION
1 Power supply for REF. 3.3V
48 Power supply for IOAPIC0, 2.5V.
25 Power supply for core logic. 3.3V
41,45
Power supply for CPUCLK1T and CPUCLK0T,
CPUCLK1T, IOAPIC0, 2.5V.
17 Power supply for AGP outputs.
11 Power supply for PCI outputs.
36 Power supply for SDRAM and 48/24MHz outputs.
21 Power supply for 48/24MHz outputs.
4,5,8,14,20,26,46,39,42 Circuit Ground.
Publication Release Date: April. 2001
- 5 - Revision 1.0
5 Page 
W83194BR-640
6.2.5 Register 8: Control Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 X 23 Latched AGPSEL#
6 X 10 Latched FS3#
5 X 9 Latched FS2#
4 X 3 Latched FS1#
3 X 2 Latched FS0#
2 1 - ACskew2 (AGP to CPU skew program bit)
1 0 - ACskew1 (AGP to CPU skew program bit)
0 0 - ACskew0 (AGP to CPU skew program bit)
6.2.6 Register 9: SDRAM Register(1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 1 - CPUCLK1 Free-run Control 1=CPUCLK1 can stopped by
CPU_STOP# , 0= CPUCLK1 Free-run
5 1 - Reserved
4 X - Latched AGP_STOP#
3 X - Latched CPU_STOP#
2 X - Latched PCI_STOP#
1 X - Latched SDR_STOP#
0 X - Latched PD#
6.2.7 Register 10: Watchdog Timer Register
Bit @PowerUp Pin
Description
7 0 - Enable Count 1 = start timer
0 = stop timer
6 X - Second timeout status (READ ONLY)
5 0 - Second count 5
4 0 - Second count 4
3 0 - Second count 3
2 0 - Second count 2
1 0 - Second count 1
0 0 - Second count 0
- 11 -
Publication Release Date: April. 2001
Revision 1.0
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet W83194BR-640.PDF ] | |
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