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PDF 56F827 Data sheet ( Hoja de datos )
| Número de pieza | 56F827 | |
| Descripción | 16-bit Digital Signal Processor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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56F827
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F827
Rev. 12
01/2007
freescale.com
1 page  
56F827 Description
• One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)
• One 8-channel Programmable Chip Select
• Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)
• Computer-Operating Properly (COP) Watchdog timer
• Two external interrupt pins
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the core clock
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• One Time of Day (TOD) Timer
1.1.4 Power Information
• Dual power supply, 3.3V and 2.5V
• Wait and Multiple Stop modes available
1.2 56F827 Description
The 56F827 is a member of the 56800 core-based family of controllers. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F827 is well-suited for many applications.
The 56F827 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
This controller also provides a full set of standard programmable peripherals that include one 10-input,
12-bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
Freescale Semiconductor
56F827 Technical Data, Rev. 12
5
5 Page 
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
VPP
Pin No.
90
EXTAL
59
Type
Input
Input
Description
VPP—This pin should be left unconnected as an open circuit for normal
functionality.
External Crystal Oscillator Input—This input should be connected to a
4MHz external crystal or ceramic resonator. For more information, please refer
to Section 3.6.
XTAL
60
(CLOCKIN)
CLKO
57
Output
Input
Output
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.6.3.
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.6.3.
External Clock Input—This input should be used when using an external
clock or ceramic resonator.
Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock
at the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
Freescale Semiconductor
56F827 Technical Data, Rev. 12
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56F827.PDF ] | |
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