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PDF HY5V26CLF Data sheet ( Hoja de datos )
| Número de pieza | HY5V26CLF | |
| Descripción | (HY5V26CxF) 4 Banks X 2M X 16bits Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
Preliminary
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device balls are compatible with LVTTL interface
• 54Ball FBGA (10.5mm x 8.3mm)
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Internal four banks operation
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY5V26CF-6
HY5V26CF-K
HY5V26CF-H
HY5V26CF-8
HY5V26CF-P
HY5V26CF-S
HY5V26C(L/S)F-6
HY5V26C(L/S)F-K
HY5V26C(L/S)F-H
HY5V26C(L/S)F-8
HY5V26C(L/S)F-P
HY5V26C(L/S)F-S
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power Organization
Normal
4Banks x 2Mbits
x16
Low power
Interface
LVTTL
Package
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 0.9/Jul. 02
2
1 page  
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ABSOLUTE MAXIMUM RATINGS
HY5V26C(L/S)F
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any ball relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
Soldering Temperature ⋅ Time
Symbol
TA
TSTG
VIN, VOUT
VDD, VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260 ⋅ 10
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol Min Typ
Power Supply Voltage
Input High voltage
Input Low voltage
VDD, VDDQ
VIH
VIL
3.0 3.3
2.0 3.0
-0.3 0
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
Max
3.6
VDDQ + 0.3
0.8
Unit
°C
°C
V
V
mA
W
°C ⋅ Sec
Unit Note
V1
V 1,2
V 1,3
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
Note
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.9/Jul. 02
6
5 Page 
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VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I(mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
HY5V26C(L/S)F
20
15
10
5
0
0
Minimum VDD clamp current
(Referenced to VDD)
12
Voltage
I (mA)
3
-3
0
-10
-20
-30
-40
-50
-60
Minimum VSS clamp current
-2.5 -2 -1.5 -1 -0.5
Voltage
I (mA)
0
Rev. 0.9/Jul. 02
12
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