|
|
PDF AD8339 Data sheet ( Hoja de datos )
| Número de pieza | AD8339 | |
| Descripción | Quad I/Q Demodulator And Phase Shifter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD8339 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
DC to 50 MHz, Quad I/Q Demodulator
and Phase Shifter
AD8339
FEATURES
Quad integrated I/Q demodulator
16 phase select on each output (22.5° per step)
Quadrature demodulation accuracy
Phase accuracy: ±1°
Amplitude imbalance: ±0.05 dB
Bandwidth
4LO: LF to 200 MHz
RF: LF to 50 MHz
Baseband: determined by external filtering
Output dynamic range: 160 dB/Hz
LO drive: >0 dBm (50 Ω), single-ended sine wave
Supply: ±5 V
Power consumption: 73 mW/channel (290 mW total)
Power-down via SPI (each channel and complete chip)
APPLICATIONS
Medical imaging (CW ultrasound beamforming)
Phased array systems
Radar
Adaptive antennas
Communication receivers
GENERAL DESCRIPTION
The AD83391 is a quad I/Q demodulator configured to be
driven by a low noise preamplifier with differential outputs. It is
optimized for the LNA in the AD8332/AD8334/AD8335 family
of VGAs. The part consists of four identical I/Q demodulators
with a 4× local oscillator (LO) input that divides the signal and
generates the necessary 0° and 90° phases of the internal LO
that drive the mixers. The four I/Q demodulators can be used
independently of each other (assuming that a common LO is
acceptable) because each has a separate RF input.
Continuous wave (CW) analog beamforming (ABF) and I/Q
demodulation are combined in a single 40-lead, ultracompact
chip scale device, making the AD8339 particularly applicable in
high density ultrasound scanners. In an ABF system, time
domain coherency is achieved following the appropriate phase
alignment and summation of multiple receiver channels. A reset
pin synchronizes multiple ICs to start each LO divider in the
same quadrant. Sixteen programmable 22.5° phase increments
are available for each channel. For example, if Channel 1 is used
as a reference and Channel 2 has an I/Q phase lead of 45°, the
user can phase align Channel 2 with Channel 1 by choosing the
appropriate phase select code.
1 Protected by U.S. Patent Number 7,760,833.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
RF1N RF1P
AD8339
RSTS
SCLK
SDI
SDO
CSB
RF2P
RF2N
4LOP
4LON
RF3P
RF3N
VPOS
VNEG
SERIAL
INTERFACE
0°
÷4 90°
BIAS
Φ I1OP
Φ Q1OP
Φ I2OP
Φ Q2OP
Φ I3OP
Φ Q3OP
Φ I4OP
Φ Q4OP
RF4N RF4P
Figure 1.
The mixer outputs are in current form for convenient summa-
tion. The independent I and Q mixer output currents are summed
and converted to a voltage by a low noise, high dynamic range,
current-to-voltage (I-V) transimpedance amplifier, such as the
AD8021 or the AD829. Following the current summation, the
combined signal is applied to a high resolution analog-to-digital
converter (ADC), such as the AD7665 (16-bit, 570 kSPS).
An SPI-compatible serial interface port is provided to easily
program the phase of each channel; the interface allows daisy
chaining by shifting the data through each chip from SDI to SDO.
The SPI also allows for power-down of each individual channel
and the complete chip. During power-down, the serial interface
remains active so that the device can be programmed again.
The dynamic range is typically 160 dB/Hz at the I and Q
outputs. The AD8339 is available in a 6 mm × 6 mm, 40-lead
LFCSP and is specified over the industrial temperature range of
−40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
1 page  
AD8339
Data Sheet
Parameter
Test Conditions/Comments
Min Typ Max Unit
LOGIC INTERFACES
Pin SDI, Pin CSB, Pin SCLK, Pin RSET
Logic Level High
1.5 V
Logic Level Low
0.9 V
Pin RSTS
Logic Level High
1.8 V
Logic Level Low
1.2 V
Bias Current
Logic high (pulled to 5 V)
0.5 μA
Logic low (pulled to GND)
0 μA
Input Resistance
4 MΩ
LO Divider RSET Setup Time
RSET rising or falling edge to 4LOP or 4LON (differential) 5
rising edge
ns
LO Divider RSET High Pulse Width
20 ns
LO Divider RSET Response Time
200 ns
Phase Response Time
Measured from CSB going high
5 μs
Enable Response Time
Measured from CSB going high (with 0.1 μF capacitor on
Pin LODC); no channel enabled
12 15 μs
At least one channel enabled
500 ns
Output
Pin SDO loaded with 5 pF and next SDI input
Logic Level High
1.7 1.9
V
Logic Level Low
0.2 0.5 V
SPI TIMING CHARACTERISTICS
Pin SDI, Pin SDO, Pin CSB, Pin SCLK, Pin RSTS
SCLK Frequency
fCLK
10 MHz
CSB Fall to SCLK Setup Time
t1
0 ns
SCLK High Pulse Width
t2
10 ns
SCLK Low Pulse Width
t3
10 ns
Data Access Time (SDO) After SCLK
Rising Edge
t4
100 ns
Data Setup Time Before SCLK Rising t5
Edge
2 ns
Data Hold Time After SCLK Rising
Edge
t6
2 ns
SCLK Rise to CSB Rise Hold Time
t7
15 ns
CSB Rise to SCLK Rise Hold Time
t8
0 ns
POWER SUPPLY
Pin VPOS, Pin VNEG
Supply Voltage
±4.5 ±5.0 ±5.5 V
Current
VPOS, all phase bits = 0
35 mA
VNEG, all phase bits = 0
−18 mA
Over Temperature,
−40°C < TA < +85°C
VPOS, all phase bits = 0
33 36 mA
VNEG, all phase bits = 0
−19 −17 mA
Quiescent Power
Per channel, all phase bits = 0
66 mW
Per channel maximum (depends on phase bits)
88 mW
Disable Current
All channels disabled; SPI stays on
2.75 mA
PSRR
VPOS to Ix/Qx outputs, @ 10 kHz
−85 dB
VNEG to Ix/Qx outputs, @ 10 kHz
−85 dB
Rev. B | Page 4 of 36
5 Page 
AD8339
1.4
I OUTPUT OF CHANNEL 1 SHOWN
TRANSCONDUCTANCE = [(VBB/787Ω)/VRF]
1.3
1.2
1.1
1.0
PHASE DELAY = 0°
0.9 PHASE DELAY = 22.5°
PHASE DELAY = 45°
PHASE DELAY = 67.5°
0.8
1M
10M
RF FREQUENCY (Hz)
Figure 21. Transconductance vs. RF Frequency
for First Quadrant Phase Delays
50M
10
+85°C
0 +25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON-MODE VOLTAGE (V)
Figure 22. LO Common-Mode Range at Three Temperatures
20
18
16
14
12
10
8
6
4
2
0
1M 10M 50M
RF FREQUENCY (Hz)
Figure 23. Representative Range of IP1dB vs. RF Frequency,
Baseband Frequency = 10 kHz, First Quadrant (See Figure 43)
Data Sheet
0
–10 0dBm
–20 3 8 13 18
IM3 PRODUCTS
LO = 5.023MHz
–30 RF1 = 5.015MHz
RF2 = 5.010MHz
–40
–50
–60
–70
1M
10M 50M
RF FREQUENCY (Hz)
Figure 24. Representative Range of IM3 vs. RF Frequency, First Quadrant
(See Figure 49)
35
30
25
20
15
10
5
0
1M 10M 50M
RF FREQUENCY (Hz)
Figure 25. Representative Range of OIP3 vs. RF Frequency, First Quadrant
(See Figure 49)
35
30
25
20
15
10
5
0
1k 10k 100k
BASEBAND FREQUENCY (Hz)
Figure 26. Representative Range of OIP3 vs. Baseband Frequency
(See Figure 48)
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8339.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD8330 | Variable Gain Amplifier | Analog Devices |
| AD8331 | Ultralow Noise VGAs | Analog Devices |
| AD8332 | Ultralow Noise VGAs | Analog Devices |
| AD8333 | Dual I/Q Demodulator and Phase Shifter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |