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UD61466 fiches techniques PDF

ZMD - DRAM

Numéro de référence UD61466
Description DRAM
Fabricant ZMD 
Logo ZMD 





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UD61466 fiche technique
Maintenance only
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UD61466
64K x 4 DRAM
Features
SCM facilitates faster data operation Data Output Control
F with predefined row address. Via 8 The usual state of the data output is
Dynamic random access memory address inputs the 16 address bits the High-Z state. Whenever CAS is
65536 x 4 bits manufactured
are transmitted into the internal inactive (HIGH), Q will float (High-Z).
using a CMOS technology
F RAS access times 70 ns/80 ns
F TTL-compatible
F Three-state outputs bidirectional
F 256 refresh cycles
address memories in a time-multi- Thus, CAS functions as data output
plex operation. The falling RAS- control.
edge takes over the row address. After access time, in case of a Read
After the row address hold time the cycle, the output is activated, and it
column address can be applied. contains the logic „0“ or „1“.
4 ms refresh cycle time
F STATIC COLUMN MODE
F Operating modes: Read, Write,
During the Read cycle the address The memory cycle being a Read,
transfer is not latched by the falling Read-Write or a Write cycle (W-con-
edge at the CAS input, so that the trolled), Q changes from High-Z
Read - Write,
column address must be applied state to the active state („0“ or „1“).
RAS only Refresh,
until the data are valid at the output. After access time, the contents of
Hidden Refresh with address
During Write the column address is the selected cell will be available,
transfer
F Low power dissipation
F Power supply voltage 5 V
F Package PDIP18 (300 mil)
F Operating temperature range
taken over with the falling edge of with the exception of the Write cycle.
the control signal CAS, or W, that The output remains active until CAS
becomes active as the last. The sel- becomes inactive, irrespective of
ection of one or more memory cir- RAS becoming inactive or not. The
cuits can be made via the RAS memory cycle being a Write cycle
F 0 to 70 °C
input.
Quality assessment according to
(CAS-controlled), the data output
keeps its High-Z state throughout
CECC 90000, CECC 90100 and Read-Write-Control
the whole cycle. This configuration
CECC 90112
The choice between Read or Write makes Q fully controllable by the
cycle is made at the W input. HIGH user merely through the timing of W.
Description
at the W input causes a Read cycle, The output storaging the data, they
meanwhile LOW leads to a Write remain valid from the end of access
Addressing
cycle.
time until the start of another cycle.
The UD61466 is a dynamic random Both CAS-controlled and W-control-
access memory organized 65536 led Write cycles are possible with
words by 4 bits.
activated RAS signal.
Pin Configuration
Pin Description
(OE)
(WE)
G
DQ0
DQ1
W
RAS
A0
A2
A1
VCC
1 18
2 17
3 16
4 15
5
PDIP
SOJ
14
6 13
7 12
8 11
9 10
VSS
DQ3
CAS
DQ2
A6
A3
A4
A5
A7
Top View
Signal Name
A0 - A7
DQ0 - DQ3
W
RAS
G
VCC
VSS
CAS
Signal Description
Address Inputs
Data In/Out
Read, Write Control
Row Address Strobe
Output Enable
Power Supply Voltage
Ground
Column Address Strobe
December 12, 1997
1

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