PDF HY5PS1G831F Data sheet ( Hoja de datos )

Número de pieza	HY5PS1G831F
Descripción	(HY5PS1G431F / HY5PS1G831F) 1Gb DDR2 SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F 1Gb DDR2 SDRAM HY5PS1G431(L)F HY5PS1G831(L)F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Apr. 2004 1 1 page www.DataSheet4U.com 1. Description HY5PS1G431(L)F HY5PS1G831(L)F 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD=1.8V • VDDQ=1.8V +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 3, 4, 5 and 6 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • Internal 8 bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 60ball FBGA(x4/x8) • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Read Data Strobe suupported (x8 only) • Self-Refresh High Temperature Entry Ordering Information Operating Frequency Part No. HY5PS1G431(L)F-X* HY5PS1G831(L)F-X* Configuration Package 256Mx4 128Mx8 68Ball Note: -X* is the speed bin, refer to the Operation Frequency table for complete Part No. Grade tCK(ns) -E3 5 -E4 5 -C4 3.75 -C5 3.75 -Y5 3 -Y6 3 CL 3 4 4 5 5 6 tRCD 3 4 4 5 5 6 tRP 3 4 4 5 5 6 Unit Clk Clk Clk Clk Clk Clk Rev 0.2 / Apr. 2004 5 5 Page www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F 2.2 Functional Block Diagram 2.2.1 Functional Block Diagram(256Mx4) 8Banks x 32Mbit x 4 I/O DDR2 SDRAM refresh Self refresh logic & timer CLK CLK CKE CS RAS CAS Internal Row Counter Row Active ODT control Row Pre Decoders refresh 32Mx4 Bank7 32Mx4 Bank6 32Mx4 Bank5 32Mx4 Bank4 32Mx4 Bank3 32Mx4 Bank2 32Mx4 Bank1 32Mx4 Bank0 Memory Cell Array WE DM ODT A0 A1 Column Active bank select Column Active latch Additive Latency Column Add Counter&latch Sense Amp 16 & I/O Gate Column decoders Column Pre Decoders CLK DLL ODT control OCD DLL Clk Control 4 Output Buffers & ODT 4bit pre-fetch Read Data Register 4bit pre-fetch Write Data Register DQ 0~3 4 Input Buffers DS Address Registers A13 BA2 BA1 Mode BA0 Register DQS I/O Buffer DS DQS DQS DLL Clk OCD Control Rev 0.2 / Apr. 2004 11 11 Page

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