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PDF HY5PS1G821L Data sheet ( Hoja de datos )
| Número de pieza | HY5PS1G821L | |
| Descripción | (HY5PS1G421 / HY5PS1G821) 1Gb DDR2 SDRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY5PS1G421(L)M
HY5PS1G821(L)M
1Gb DDR2 SDRAM(DDP)
HY5PS1G421(L)M
HY5PS1G821(L)M
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev 0.1 / Mar. 2004
1
1 page  
www.DataSheet4U.com
1. Description
HY5PS1G421(L)M
HY5PS1G821(L)M
1.1 Device Features & Ordering Information
1.1.1 Key Features
• Dual Die Package( 512Mb DDR2 * 2)
• VDD, VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal 4 bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe suupported (x8 only)
• Self-Refresh High Temperature Entry
Ordering Information
Operating Frequency
Part No.
HY5PS1G421(L)M-X*
HY5PS1G821(L)M-X*
Configuration Package
256Mx4
128Mx8
63Ball
Note: -X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
Grade tCK(ns)
-E3 5
-E4 5
-C4 3.75
-C5 3.75
-Y5 3
-Y6 3
CL
3
4
4
5
5
6
tRCD
3
4
4
5
5
6
tRP
3
4
4
5
5
6
Unit
Clk
Clk
Clk
Clk
Clk
Clk
Rev 0.1 / Mar. 2004
5
5 Page 
www.DataSheet4U.com
2.2 Functional Block Diagram
2.2.1 Block Diagram(DDP. 256Mx4)
CLK, /RAS, /CAS
/WE, DM
CKE1
/CS1
ODT1
CKE0
/CS0
ODT0
HY5PS1G421(L)M
HY5PS1G821(L)M
128Mx4
128Mx4
DQ0 ~ DQ3
A0~A13,BA0,BA1
2.2.2 Block Diagram(DDP. 128Mx8)
CLK, /RAS, /CAS
/WE, DM
CKE1
/CS1
ODT1
CKE0
/CS0
ODT0
64Mx8
64Mx8
Rev 0.1 / Mar. 2004
DQ0 ~ DQ7
A0~A13,BA0,BA1
11
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| Páginas | Total 30 Páginas | |
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