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PDF KSZ8995M Data sheet ( Hoja de datos )
| Número de pieza | KSZ8995M | |
| Descripción | Integrated 5-Port 10/100 Managed Switch | |
| Fabricantes | Micrel Semiconductor | |
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KS8995M
www.DataSheet4U.com
Micrel
KS8995M
Integrated 5-Port 10/100 Managed Switch
Rev 1.12
General Description
The KS8995M is a highly integrated Layer-2 managed switch
with optimized BOM (Bill of Materials) cost for low port count,
cost-sensitive 10/100Mbps switch systems. It also provides
an extensive feature set such as tag/port-based VLAN, QoS
(Quality of Service) priority, management, MIB counters, dual
MII interfaces and CPU control/data interfaces to effectively
address both current and emerging Fast Ethernet applica-
tions.
The KS8995M contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five MAC (Media
Access Control) units, a high-speed non-blocking switch
fabric, a dedicated address look-up engine, and an on-chip
frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,
two of the PHY units support 100BaseFX (Ports 4 and 5).
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Functional Diagram
Features
• Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non-
blocking configuration
• 1.4Gbps high-performance memory bandwidth
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in
Ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode
MII) and MII-P5 (PHY mode MII)
• IEEE 802.1q tag-based VLAN (16 VLANs, full-range
VID) for DMZ port, WAN/LAN separation or inter-VLAN
switch links
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting 0Mbps to 100Mbps, ingress
and egress port, rate options for high and low priority,
per-port-basis
• Flow control or drop packet rate limiting (ingress port)
• Integrated MIB counters for fully compliant statistics
gathering, 34 MIB counters per port
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-P5
MDC, MDI/O
MII-SW or SNI
Control Reg I/F
LED0[5:1]
LED1[5:1]
LED2[5:1]
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
LED I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
SPI
Control
Registers
1K look-up
Engine
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
MIB
Counters
EEPROM
I/F
KS8995M
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
December 2003
1
M9999-120403
1 page  
KS8995M
Micrel
Register Description ................................................................................................................................................. 39
Global Registers .................................................................................................................................................. 39
Register 0 (0x00): Chip ID0 ......................................................................................................................... 39
Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39
Register 2 (0x02): Global Control 0 ............................................................................................................. 40
Register 3 (0x03): Global Control 1 ............................................................................................................. 40
Register 4 (0x04): Global Control 2 ............................................................................................................. 41
Register 5 (0x05): Global Control 3 ............................................................................................................. 42
Register 6 (0x06): Global Control 4 ............................................................................................................. 42
Register 7 (0x07): Global Control 5 ............................................................................................................. 43
Register 8 (0x08): Global Control 6 ............................................................................................................. 43
Register 9 (0x09): Global Control 7 ............................................................................................................. 43
Register 10 (0x0A): Global Control 8 ........................................................................................................... 43
Register 11 (0x0B): Global Control 9 ........................................................................................................... 43
Port Registers ...................................................................................................................................................... 44
Register 16 (0x10): Port 1 Control 0 ........................................................................................................... 44
Register 17 (0x11): Port 1 Control 1 ........................................................................................................... 44
Register 18 (0x12): Port 1 Control 2 ........................................................................................................... 45
Register 19 (0x13): Port 1 Control 3 ........................................................................................................... 46
Register 20 (0x14): Port 1 Control 4 ........................................................................................................... 46
Register 21 (0x15): Port 1 Control 5 ........................................................................................................... 46
Register 22 (0x16): Port 1 Control 6 ........................................................................................................... 46
Register 23 (0x17): Port 1 Control 7 ........................................................................................................... 46
Register 24 (0x18): Port 1 Control 8 ........................................................................................................... 47
Register 25 (0x19): Port 1 Control 9 ........................................................................................................... 47
Register 26 (0x1A): Port 1 Control 10 ......................................................................................................... 47
Register 27 (0x1B): Port 1 Control 11 ......................................................................................................... 47
Register 28 (0x1C): Port 1 Control 12 ......................................................................................................... 48
Register 29 (0x1D): Port 1 Control 13 ......................................................................................................... 49
Register 30 (0x1E): Port 1 Status 0 ............................................................................................................ 49
Register 31 (0x1F): Port 1 Status 1 ............................................................................................................. 50
Advanced Control Registers ................................................................................................................................ 50
Register 96 (0x60): TOS Priority Control Register 0 ................................................................................... 50
Register 97 (0x61): TOS Priority Control Register 1 ................................................................................... 50
Register 98 (0x62): TOS Priority Control Register 2 ................................................................................... 50
Register 99 (0x63): TOS Priority Control Register 3 ................................................................................... 50
Register 100 (0x64): TOS Priority Control Register 4 ................................................................................. 50
Register 101 (0x65): TOS Priority Control Register 5 ................................................................................. 50
Register 102 (0x66): TOS Priority Control Register 6 ................................................................................. 50
Register 103 (0x67): TOS Priority Control Register 7 ................................................................................. 50
Register 104 (0x68): MAC Address Register 0 ........................................................................................... 50
Register 105 (0x69): MAC Address Register 1 ........................................................................................... 50
Register 106 (0x6A): MAC Address Register 2 ........................................................................................... 50
Register 107 (0x6B): MAC Address Register 3 ........................................................................................... 50
Register 108 (0x6C): MAC Address Register 4 .......................................................................................... 50
Register 109 (0X6D): MAC Address Register 5 .......................................................................................... 50
Register 110 (0x6E): Indirect Access Control 0 .......................................................................................... 51
Register 111 (0x6F): Indirect Access Control 1 .......................................................................................... 51
December 2003
5
M9999-120403
5 Page 
KS8995M
Micrel
Pin Number
59
60
61
62
63
64
65
Pin Name
VDDIO
PMRXC
PMRXDV
PMRXD3
PMRXD2
PMRXD1
PMRXD0
66 PMRXER
67 PCRS
68 PCOL
69 SMTXEN
70 SMTXD3
71 SMTXD2
72 SMTXD1
73 SMTXD0
74 SMTXER
75 SMTXC
76 GNDD
77 VDDIO
78 SMRXC
79 SMRXDV
80 SMRXD3
81 SMRXD2
Type(1)
P
O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
Gnd
P
I/O
Ipd/O
Ipd/O
Ipd/O
Port
5
5
5
5
5
5
5
5
5
Pin Function
3.3/2.5V digital VDD for digital I/O circuitry
PHY[5] MII receive clock. PHY mode MII
PHY[5] MII receive data valid
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
PHY[5] MII carrier sense/Force duplex mode. See “Register 76” for
port 4 only. PD (default) = Force half-duplex if auto-negotiation is
disabled or fails. PU = Force full-duplex if auto-negotiation is disabled
or fails.
PHY[5] MII collision detect/ Force flow control. See “Register 66” for
port 4 only. PD (default) = No force flow control. PU = Force flow
control.
Switch MII transmit enable
Switch MII transmit bit 3
Switch MII transmit bit 2
Switch MII transmit bit 1
Switch MII transmit bit 0
Switch MII transmit error
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
Digital ground
3.3/2.5V digital VDD for digital I/O circuitry
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
Switch MII receive data valid
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
December 2003
11
M9999-120403
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8995M.PDF ] | |
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