|
|
PDF MAX3964A Data sheet ( Hoja de datos )
| Número de pieza | MAX3964A | |
| Descripción | 125Mbps to 266Mbps Limiting Amplifiers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX3964A (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
19-1314; Rev 5; 8/06
EVAALVUAAILTAIOBNLEKIT
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
General Description
The MAX3969 is a recommended upgrade for the
MAX3964 and MAX3968. The MAX3964A limiting amplifi-
er, with 2mVP-P input sensitivity and PECL data outputs, is
ideal for low-cost ATM, FDDI, and Fast Ethernet fiber
optic applications.
The MAX3964A features an integrated power detector
that senses the input-signal power. It provides a
received-signal-strength indicator (RSSI), which is an
analog indication of the power level and complementary
PECL loss-of-signal (LOS) outputs, which indicate when
the power level drops below a programmable threshold.
The threshold can be adjusted to detect signal ampli-
tudes as low as 2.7mVP-P. An optional squelch function
disables switching of the data outputs by holding them at
a known state during an LOS condition.
The MAX3968 provides the same functionality as the
MAX3964A, but has data-output edge speed suitable for
ESCON and 266Mbps fibre channel applications.
The MAX3964A/MAX3968 are available in die form, as
tested wafers, and in 20-pin QSOP packages. The
MAX3964AETP is available in a 20-pin thin QFN package.
Applications
125Mbps FDDI Receivers
155Mbps LAN ATM Receivers
Fast Ethernet Receivers
ESCON Receivers
155Mbps FTTx Receivers
Features
♦ Single Supply: +3.0V to +5.5V
♦ 2mVP-P Input Sensitivity
♦ 1.2ns Output Edge Speed
♦ Loss-of-Signal Detector with Programmable
Threshold
♦ Analog Received-Signal-Strength Indicator
♦ Output Squelch Function
♦ Compatible with 4B/5B Data Coding
Ordering Information
PART
MAX3964AETP
MAX3964AETP+
MAX3964AC/D
MAX3968CEP
MAX3968C/D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
20 Thin QFN**
20 Thin QFN**
Dice*
20 QSOP
Dice*
*Dice are designed to operate over a 0°C to +100°C junction
temperature (Tj) range, but are tested and guaranteed only at TA
= +25°C.
**Package Code: T2044-1
+Denotes lead-free package.
Pin Configurations and Selector Guide appear at end of data
sheet.
Typical Operating Circuit
VCC
0.1µF
VCC
VCC
PHOTODIODE
IN
VCC
155Mbps
TIA
OUT-
OUT+
GND
FILTER
10nF
VCC
FILTER
CZP
CZN
RSSI
SQUELCH
CIN
4700pF
VCC0 LOS+
LOS-
MAX3964A
IN- MAX3968 OUT-
CIN
4700pF
R1
≥100kΩ
IN+
INV
OUT+
SUB*
GND
VTH
R2
CAZ
1µF
50Ω
50Ω
50Ω
50Ω
VCC - 2V
*PIN NOT AVAILABLE ON MAX3964AETP.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
PIN
QSOP
THIN
QFN
1 19
2 20
31
42
5
6
7
8
9, 10
11
3
4
5
—
6, 7, 8
9
12 10
13 11
14 12
15 13
16 14
17 15
18
19, 20
16
17, 18
— EP
Pin Description
NAME
FUNCTION
SQUELCH
Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+
high during a loss-of-signal condition. Connect to GND or leave unconnected to disable.
Connect to VCC to enable squelching.
Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a
VTH resistor from VTH to INV and from INV to ground (minimum resistance 100kΩ) to program the
desired threshold voltage.
Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1).
INV Connect a resistor from VTH to INV and from INV to ground (minimum resistance 100kΩ) to
program the desired threshold voltage.
FILTER
RSSI
IN-
Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed
together at FILTER to generate the received-signal-strength indicator (RSSI). Connect a
capacitor from FILTER to VCC for proper operation.
Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input
signal power. The RSSI output is reduced approximately 120mV when LOS+ is asserted.
Inverting Data Input
IN+ Noninverting Data Input
SUB
Substrate. Connect to ground.
GND
CZP
CZN
VCCO
OUT+
OUT-
LOS-
LOS+
VCCO
VCC
Exposed
Pad
Ground
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
Output Buffer Supply Voltage. Connect to the same potential as VCC, but filter VCCO and VCC
separately.
Noninverting PECL Data Output. Terminate with 50Ω to (VCC - 2V).
Inverting PECL Data Output. Terminate with 50Ω to (VCC - 2V).
Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS
threshold. This pin is PECL compatible and should be terminated with 50Ω to (VCC - 2V).
Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the
LOS threshold. This pin is PECL compatible and should be terminated with 50Ω to (VCC - 2V).
MAX3964A/MAX3968: This pin can be left open or connected to the positive supply.
+3.0V to +5.5V Supply Voltage
Connect the exposed pad to board ground for optional electrical and thermal performance.
_______________________________________________________________________________________ 5
5 Page 
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
Rev 0;
Rev 1;
Rev 2;
Rev 3;
Rev 4;
Rev 5;
10/98:
10/02:
5/03:
9/04:
2/06:
8/06:
Revision History
Initial data sheet release.
Added MAX3964ETP.
Added package code for TQFN (page 1); updated package drawing (pages 11, 12).
Added MAX3964A (pages 1 to 13).
Added lead-free package information to Ordering Information table (page 1).
Removed references to MAX3964 and MAX3965, TTL Loss of Signal, GNDO; updated CAZ
value to 0.1µF and CIN from 10nF to 4700pF. Updated Typical Application Circuit.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MAX3964A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX3964 | (MAX3964 - MAX3968) 125Mbps to 266Mbps Limiting Amplifiers | Maxim Integrated Products |
| MAX3964A | 125Mbps to 266Mbps Limiting Amplifiers | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |