PDF VSC8111 Data sheet ( Hoja de datos )

Número de pieza	VSC8111
Descripción	ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux
Fabricantes	Vitesse Semiconductor
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No Preview Available ! Data Sheet VSC8111 www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Features • Operates at Either STS-3/STM-1 (155.52 Mb/s) or STS-12/STM-4 (622.08 Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52 Mhz or 622.08 Mhz High Speed Clock • Dual 8 Bit Parallel TTL Interface • Loss of Signal (LOS) Control • Provides Equipment, Facilities and Split Loop- back Modes as well as Loop Timing Mode • Meets Bellcore, ITU and ANSI Speciﬁcations for Jitter Performance • Single 3.3V Supply Voltage • Low Power - 1.4 Watts Maximum • SONET/SDH Frame Detection and Recovery • 100 PQFP Package General Description The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip- ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for ATM physical layers and SONET/SDH systems applications. VSC8111 Block Diagram EQULOOP LOSTTL LOSPOL LOS (Internal Signal) RXDATAIN+/- DQ RXCLKIN+/- 0 1 FRAMER OOF FP 0 1:8 8 DEMUX DQ RXOUT[7:0] 1 0 Divide-by-8 1 RXLSCKOUT TXDATAOUT+/- TXCLKOUT+/- FACLOOP QD 1 0 1 0 10 8:1 MUX 8 QD Divide-by-8 TXIN[7:0] TXLSCKIN TXLSCKOUT Divide-by-3/12 RX50MCK LOOPTIM0 CMU 1 0 REFCLK LOOPTIM1 LOS EQULOOP G52142-0, Rev 4.2 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 1 page Data Sheet VSC8111 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output (TXDATAOUT) along with the high speed transmit clock (TXCLKOUT) which is generated by the on board clock multiplier unit. Figure 4: Equipment Loopback Data Path RXDATAIN RXCLKIN TXDATAOUT EQULOOP TXCLKOUT DQ QD 0 1:8 Serial to 1 Parallel 0 ÷8 1 8:1 Parallel to Serial DQ QD PLL ÷ 8 RXOUT[7:0] RXLSCKOUT TXIN[7:0] TXLSCKIN TXLSCKOUT Split Loopback Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized and presented to RXOUT[0:7] and TXIN[0:7] will not be serialized and present to TXDATAOUT. Figure 5: Split Loopback Datapath RXDATAIN RXCLKIN TXDATAOUT TXCLKOUT FACLOOP DQ QD 1 0 1 0 0 1:8 Serial to Parallel 1 0 ÷8 1 8:1 Parallel to Serial PLL DQ QD RXOUT[7:0] RXLSCKOUT TXIN[[7:0] TXLSCLKIN EQULOOP G52142-0, Rev 4.2 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 5 Page Data Sheet VSC8111 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation TXCLKOUT- TXCLKOUT+ TXDATAOUT+ TXDATAOUT- Figure 10: Transmit High Speed Data Timing Diagram TTXCLK TSKEW TSKEW Table 10: Transmit High Speed Data Timing Table (STS-12 Operation) Parameter TTXCLK TSKEW Description Transmit clock period Skew between the falling edge of TXCLKOUT+ and valid data on TXDATAOUT Min - - Typ 1.608 - Max - 250 Units ns ps Table 11: Transmit High Speed Data Timing Table (STS-3 Operation) Parameter TTXCLK TSKEW Description Transmit clock period Skew between the falling edge of TXCLKOUT+ and valid data on TXDATAOUT Min Typ Max Units - 6.43 - ns - - 250 ps Data Latency The VSC8111 contains several operating modes, each of which exercise different logic paths through the part. Table 12 bounds the data latency through each path with an associated clock signal. Table 12: Data Latency Circuit Mode Description Transmit Receive Equipment Loopback Facilities Loopback Data TXIN [7:0] to MSB at TXDATAOUT MSB at RXDATAIN to data on RXOUT [7:0] Byte data TXIN [7:0] to byte data on RXOUT [7:0] MSB at RXDATAIN to MSB at TXDATAOUT Clock Reference TXCLKOUT RXCLKIN TXCLKOUT RXCLKIN Range of Clock cycles 4-13 24-32 27-35 2 G52142-0, Rev 4.2 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 11 Page

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