VSC7139 Datasheet PDF - Vitesse Semiconductor
| Part Number | VSC7139 | |
| Description | Quad Transceiver | |
| Manufacturers | Vitesse Semiconductor | |
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Features
• Four Complete Transmitter/ Receiver Functions
in a Single Integrated Circuit
• Full Fibre Channel (T11) and Gigabit Ethernet
(IEEE 802.3z) Compliance
• 1.05Gb/s to 1.36Gb/s Operation per Channel
• Common or Per-Channel Transmit Byte Clocks
• TTL or PECL Reference Clock Input
• 1/10th or 1/20th Baud Rate Recovered Clocks
• Common and Per-Channel, Serial and Paral-
lel Loopback Controls
• Common Comma Detect Enable Inputs
• Per-Channel Comma Detect Outputs
• Cable Equalization in Receivers
• Automatic Lock-to-Reference
• 3.3V Power Supply, 2.67 W Max Power
Dissipation
• 208-Pin, 23mm BGA Packaging
General Description
The VSC7139 is a full-speed Quad Fibre Channel and Gigabit Ethernet Transceiver IC. Each of the four
transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters
and serializes the data onto high speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be
synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each
receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters,
outputs a recovered clock and detects “Comma” characters. The VSC7139 contains on-chip (PLL) circuitry for
synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.
VSC7139 Block Diagram (1 of 4 Channels)
Rx(0:9)
RCM
RCx1
RCx0
SYNCx
ENCDET
PLUP
SLPN
LPNx
Tx(0:9)
TBCx
REFT
REF+
REF-
RFCM
LTCN
10
QD
Serial to
Q Parallel D
QD
Comma
Detect
Loopback
4 Control
SEL
÷10/
÷20
÷10 Clock
Recovery
0
1
10
DQ
4
4
Clock
Multiply
Unit
x10/x20
Parallel
to Serial
DQ
0
1
Rx+
Rx-
Tx+
Tx-
RFCO0
RFCO1
G52196-0, Rev 3.3
5/14/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Loopback Operation
Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNx
inputs as shown in Table 2. LPNx enables PLUP/SLPN on a per-channel basis when LOW. If LPNx is HIGH,
PLUP/SLPN have no impact on Channel x. When SLPN and PLUP are both HIGH the transmitter output is
held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the input
jitter is removed. However, the TXx outputs may not meet jitter specifications listed in the “Transmitter AC
Specifications” due to low frequency jitter transfer from RXx to TXx.
Table 2: Loopback Selection
LPNx
LOW
LOW
LOW
LOW
HIGH
PLUP
LOW
LOW
HIGH
HIGH
X
SLPN
LOW
HIGH
LOW
HIGH
X
Tranmitter Source
Receiver
Transmitter
Transmitter
HIGH
Transmitter
Receiver Source
Receiver
Receiver
Transmitter
Transmitter
Receiver
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in “VSC7139 JTAG Access Port Functionality.”
G52196-0, Rev 3.3
5/14/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Internet: www.vitesse.com
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for VSC7139 electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ VSC7139.PDF Datasheet ] | |
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