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PDF LXT386 Data sheet ( Hoja de datos )
| Número de pieza | LXT386 | |
| Descripción | QUAD T1/E1/J1 Transceiver | |
| Fabricantes | INTEL | |
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LXT386
QUAD T1/E1/J1 Transceiver
Datasheet
The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both
1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers
and four independent transmitters in a single PBGA-160 or LQFP-100 package.
The transmit drivers provide low impedance independent of the transmit pattern and supply
voltage variations.The LXT386 transmits shaped waveforms meeting G.703 and T1.102
specifications. The LXT386 exceeds the latest transmit return loss specifications, such as ETSI
ETS-300166.
The LXT386’s differential receiver architecture provides high noise interference margin and is
able to work with up to 12 dB of cable attenuation. The digital clock recovery PLL and jitter
attenuator are referenced to a low frequency 1.544 MHz or 2.048 MHz clock.
The LXT386 incorporates an advanced crystal-less jitter attenuator switchable between the
receive and transmit path. The jitter attenuation performance meets the latest international
specifications such as CTR12/13. The jitter attenuation performance was optimized for
Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/SDH) applications.
The LXT386 can be configured as a 3 channel transceiver with G.772 compliant non intrusive
protected monitoring points. It uses a single 3.3V supply for low power consumption.
The constant delay characteristic of the LXT386 JA as well as a power down mode of all
transmitters allows the implementation of Hitless Protection Switching (HPS) applications
without the use of relays.
Applications
s SONET/SDH tributary interfaces
s Digital cross connects
s Public/private switching trunk line
interfaces
s Microwave transmission systems
s M13, E1-E3 MUX
As of January 15, 2001, this document replaces the Level One document
LXT386 — QUAD T1/E1/J1 Transceiver¶ Font>.
Order Number: 249253-001
January 2001
1 page  
QUAD T1/E1/J1 Transceiver — LXT386
35 Output Jitter for CTR12/13 applications ..............................................................75
36 60 Plastic Ball Grid Array (PBGA) Package Dimensions ....................................76
37 100 Pin Low Quad Flat Packages (LQFP) Dimensions ......................................77
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Assignments and Signal Descriptions...........................................................11
Line Length Equalizer Inputs...............................................................................27
Jitter Attenuation Specifications ..........................................................................30
Operation Mode Summary ..................................................................................34
Microprocessor Parallel Interface Selection ........................................................35
Serial and Parallel Port Register Addresses .......................................................38
Register Bit Names .............................................................................................38
ID Register, ID (00H)...........................................................................................39
Analog Loopback Register, ALOOP (01H)..........................................................39
Remote Loopback Register, RLOOP (02H) ........................................................40
TAOS Enable Register, TAOS (03H) ..................................................................40
LOS Status Monitor Register, LOS (04H) ...........................................................40
DFM Status Monitor Register, DFM (05H) ..........................................................40
LOS Interrupt Enable Register, LIE (06H)...........................................................40
DFM Interrupt Enable Register, DIE (07H)..........................................................40
LOS Interrupt Status Register, LIS (08H)............................................................41
DFM Interrupt Status Register, DIS (09H)...........................................................41
Software Reset Register, RES (0AH)..................................................................41
Performance Monitoring Register, MON (0BH)...................................................41
Digital Loopback Register, DL (0CH) ..................................................................41
LOS/AIS Criteria Register, LCS (0DH)................................................................41
Automatic TAOS Select Register, ATS (0EH).....................................................42
Global Control Register, GCR (0FH)...................................................................42
Pulse Shaping Indirect Address Register, PSIAD (10H) .....................................43
Pulse Shaping Data Register, PSDAT (11H) ......................................................43
Output Enable Register, OER (12H) ...................................................................43
AIS Status Monitor Register, AIS (13H) ..............................................................43
AIS Interrupt Enable Register, AISIE (14H) ........................................................44
AIS Interrupt Status Register, AISIS (15H) .........................................................44
TAP State Description .........................................................................................46
Device Identification Register (IDR) ....................................................................50
Analog Port Scan Register (ASR) .......................................................................51
Instruction Register (IR) ......................................................................................51
Absolute Maximum Ratings.................................................................................53
Recommended Operating Conditions .................................................................53
DC Characteristics ..............................................................................................54
E1 Transmit Transmission Characteristics..........................................................55
E1 Receive Transmission Characteristics...........................................................55
T1 Transmit Transmission Characteristics ..........................................................56
T1 Receive Transmission Characteristics ...........................................................57
Jitter Attenuator Characteristics ..........................................................................58
Analog Test Port Characteristics.........................................................................59
Transmit Timing Characteristics..........................................................................59
Receive Timing Characteristics...........................................................................60
Datasheet
5
5 Page 
QUAD T1/E1/J1 Transceiver — LXT386
Table 1. Pin Assignments and Signal Descriptions
Ball #
PBGA
E1
E2
Pin #
LQFP
78
79
Symbol
MCLK
MODE
I/O1 Description
Master Clock. MCLK is an independent, free-running reference clock. It’s
frequency should be 1.544 MHz for T1 operation and 2.048 MHz for E1
operation.
This reference clock is used to generate several internal reference
signals:
• Timing reference for the integrated clock recovery unit
• Timing reference for the integrated digital jitter attenuator
• Generation of RCLK signal during a loss of signal condition
DI • Reference clock during a blue alarm transmit all ones condition
• Reference timing for the parallel processor wait state generation logic
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode,
the LXT386 operates as simple data receiver.
If MCLK is Low, the complete receive path is powered down and the
output pins RCLK, RPOS and RNEG are switched to Tri-state mode.
MCLK is not required if LXT386 is used as a simple analog front-end
without clock recovery and jitter attenuation.
Note that wait state generation via RDY/ACK is not available if MCLK is
not provided.
Mode Select. This pin is used to select the operating mode of the
LXT386. In Hardware Mode, the parallel processor interface is disabled
and hardwired pins are used to control configuration and report status.
In Parallel Host Mode, the parallel port interface pins are used to control
configuration and report status.
In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are
used.
DI
MODE
Operating Mode
L
H
Vcc/2
Hardware Mode
Parallel Host Mode
Serial Host Mode
For Serial Host Mode, the pin should connected to a resistive divider
consisting of two 10 kΩ resistors across VCC and Ground.
F4 89
A4
DI
Address Select. In host mode, this pin is Address 4 input pin. In hardware
mode this pin must be connected to Ground.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
2. N/C means “Not Connected”
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT386.PDF ] | |
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