|
|
PDF ECP2M70 Data sheet ( Hoja de datos )
| Número de pieza | ECP2M70 | |
| Descripción | ECP2/M Family | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ECP2M70 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
LatticeECP2/M Family Data Sheet
DS1006 Version 02.2, December 2006
1 page  
www.DataSheet4U.com
Lattice Semiconductor
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
Programmable
Function Units
(PFUs)
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
sysDSP Blocks
Multiply and
Accumulate Support
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysMEM Block RAM
18kbit Dual Port
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Programmable
Function Units
(PFUs)
Channel Channel
32
Channel Channel
10
DSP Blocks
Multiply & Accumulate
Support
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
sysMEM Block
RAM 18kbit Dual Port
On-Chip
Oscillator
2-2
SERDES
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysCLOCK SPLLs
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
5 Page 
www.DataSheet4U.com
Lattice Semiconductor
Architecture
LatticeECP2/M Family Data Sheet
Delay Locked Loops (DLL)
In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device.
CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes
block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference
input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated
from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI
or from tapped signal from the Delay chain.
The PFD produces a binary number proportional to the phase and frequency difference between the reference and
feedback signals. This binary output of the PFD is feed into a Arithmetic Logic Unit (ALU). Based on these inputs,
the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer-
ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL)
bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its
current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus.
The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the
outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output
to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45,
22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with
optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out-
put signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a
description of the DLL inputs and outputs.
The user can configure the DLL for many common functions such as time reference delay mode and clock injection
removal mode. Lattice provides primitives in its design tools for these functions. For more information on the DLL,
please see details of additional technical documentation at the end of this data sheet.
Figure 2-6. Delay Locked Loop Diagram (DLL)
ALUHOLD
(from routing
or external pin)
CLKI
from CLKOP (DLL
internal), from clock net
(CLKOP) or from a user
clock (pin or logic)
CLKFB
UDDCNTL
RSTN
÷4
÷2
Reference
Phase
Frequency
Detector
Feedback
Arithmetic
Logic Unit
Delay Chain
Delay0
Delay1
Delay2
Delay3
Delay4
Duty
Cycle
50%
Output
Muxes
Duty
Cycle
50%
÷4
÷2
Lock
Detect
Digital
Control
Output
9
CLKOP
CLKOS
LOCK
DCNTL
2-8
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ECP2M70.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ECP2M70 | ECP2/M Family | Lattice Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |