PDF ICS8534-01 Data sheet ( Hoja de datos )

Número de pieza	ICS8534-01
Descripción	LVPECL FANOUT BUFFER
Fabricantes	ICST
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION ICS The ICS8534-01 is a low skew, 1-to-22 Differen- tial-to-3.3V LVPECL Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™Family of High Performance Clock Solutions from ICS.The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels.The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The de- vice is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8534-01’s low output and part-to-part skew char- acteristics make it ideal for workstation, server, and other high performance clock distribution applications. FEATURES • 22 differential LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 500MHz • Output skew: 100ps (maximum) • Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input • Additive phase jitter, RMS: 0.04ps (typical) • 3.3V supply mode • 0°C to 85°C ambient operating temperature BLOCK DIAGRAM CLK_SEL CLK nCLK PCLK nPCLK OE 0 1 LE Q D PIN ASSIGNMENT 22 Q0:Q21 22 nQ0:nQ21 VCCO nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 ICS8534-01 57 25 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCCO Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VCCO 8534AY-01 64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 19, 2004 1 page Integrated Circuit Systems, Inc. ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA=0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical PCLK IIH Input High Current nPCLK VCC = VIN = 3.465V V = V = 3.465V CC IN PCLK IIL Input Low Current nPCLK VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 VPP Peak-to-Peak Input Voltage 0.3 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VOH Output High Voltage; NOTE 3 VCC - 1.4 VOL Output Low Voltage; NOTE 3 VCC - 2.0 VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCCO - 2V. Maximum 150 5 1 VCC VCC - 0.9 VCC -1.7 1.0 Units µA µA µA µA V V V V V TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA=0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum fMAX tPD tsk(o) Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 f ≤ 500MHz 2.0 500 3.0 100 tsk(pp) Part-to-Part Skew; NOTE 3, 5 Buffer Additive Phase Jitter, RMS; tjit refer to Additive Phase Jitter section; (12KHz to 20MHz) NOTE 4 0.04 tR / tF tS tH odc Output Rise/Fall Time Setup Time Hold Time Output Duty Cycle 20% to 80% f ≤ 266MHz 266 < f ≤ 500MHz 200 1.0 0.5 48 46 All parameters measured at fMAX unless noted otherwise. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 700 700 52 54 Units MHz ns ps ps ps ps ns ns % % 8534AY-01 www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 19, 2004 5 Page Integrated Circuit Systems, Inc. ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER THERMAL RELEASE PATH The exposed metal pad provides heat transfer from the device to the P.C. board. The exposed metal pad is ground pad con- nected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is con- tacted through solder as shown in Figure 6. For further informa- tion, please refer to the Application Note on Surface Mount As- sembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. SOLDER M ASK SIGNAL TRACE EXPOSED PAD SOLDER SIGNAL TRACE GROUND PLANE THERMAL VIA Expose Metal Pad (GROUND PAD) FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE 8534AY-01 www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 19, 2004 11 Page

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