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PDF ICS853210 Data sheet ( Hoja de datos )
| Número de pieza | ICS853210 | |
| Descripción | LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853210 is a low skew, high perfor-
ICS mance dual 1 - t o -5 Differential-to-2.5V/3.3V
HiPerClockS™ LVPECL/ECL Fanout Buffer and a member of
the HiPerClockS™family of High Performance
Clock Solutions from ICS. The ICS853210
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853210 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• 2 differential 2.5V/3.3V LVPECL / ECL bank outputs
• 2 differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLKx input
• Output skew: 13ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 485ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
V = 0V, V = -2.375V to -3.8V
CC EE
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP210 and MC100LVEP210
BLOCK DIAGRAM
PCLKA
nPCLKA
PCLKB
nPCLKB
VBB
853210AY
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
PIN ASSIGNMENT
VCCO
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCCO
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 ICS853210 13
29 12
30 11
31 10
32 9
1234 56 78
VCCO
QB2
nQB2
QB3
nQB3
QB4
nQB4
VCCO
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 12, 2003
1 page  
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V OR VCC = 2.375 TO 3.8V; VEE = 0V
Symbol Parameter
-40°C
25°C
85°C
Units
Min Typ Max Min Typ Max Min Typ Max
fMAX
tPLH
tPHL
tsk(o)
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Propagation Delay,
High-to-Low; NOTE 1
@ 2.5V
Output Skew; NOTE 2, 4
415
400
>3
470
470
13
>3
520 430 485
540 425 490
25 13
>3 GHz
545 435 515 585 ps
550 445 515 585 ps
25 13 25 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
85 160
85 160
85 160 ps
tR/tF Output Rise/Fall Time 20% to 80% 115 188 260 130 190 250 145 190
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
235
ps
853210AY
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 12, 2003
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853210.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
• Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power (3.8V, with all outputs switching) = 304mW + 309.4mW = 613.4mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.613W * 42.1°C/W = 110.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853210AY
www.icst.com/products/hiperclocks.html
11
REV. A NOVEMBER 12, 2003
11 Page | ||
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