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PDF ICS853111-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS853111-01 | |
| Descripción | LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853111-01 is a low skew, high perfor-
ICS mance 1-to-9 Differential-to-3.3V LVPECL/ECL
HiPerClockS™ Fa n o u t B u f f e r a n d a m e m b e r o f t h e
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The PCLK, nPCLK
pair can accept LVPECL, CML and SSTL differential input
levels.The ICS853111-01 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS853111-01 ideal for
those clock distribution applications demanding well
defined performance and repeatability.
FEATURES
• 9 differential 3.3V LVPECL / ECL outputs
• 1 differential LVPECL input pair
• PLCK, nPLCK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2GHz (typical)
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.03ps (typical)
• Output skew: 35ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 675ps (maximum)
• LVPECL mode operating voltage supply range:
V = 3V to 3.8V, V = 0V
CC EE
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.8V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
PCLK
nPCLK
V
BB
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
25 24 23 22 21 20 19
VEE 26
18 Q3
nc 27
17 nQ3
Q3 PCLK 28
16 Q4
nQ3 VCC 1 ICS853111-01 15 VCCO
Q4
nQ4
Q5
nQ5
Q6
nQ6
nPCLK 2
14 nQ4
VBB 3
13 Q5
nc 4
12 nQ5
5 6 7 8 9 10 11
Q7
nQ7 28-Lead PLCC
Q8
nQ8
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
853111AV-01
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 25, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps (typical)
10k 100k 1M
10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853111AV-01
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 25, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
• For logic high, V = V = V
– 0.935V
OUT
OH_MAX
CCO_MAX
(V - V ) = 0.935V
CCO_MAX OH_MAX
• For logic low, V = V = V
– 1.67V
OUT
OL_MAX
CCO_MAX
(V - V ) = 1.67V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OH_MAX
CCO_MAX
L CCO_MAX OH_MAX
CCO_MAX OH_MAX
L
CCO_MAX OH_MAX
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OL_MAX
CCO_MAX
L CCO_MAX OL_MAX
CCO_MAX OL_MAX
L
CCO_MAX OL_MAX
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853111AV-01
www.icst.com/products/hiperclocks.html
11
REV. A APRIL 25, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS853111-01.PDF ] | |
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