|
|
PDF ICS853052 Data sheet ( Hoja de datos )
| Número de pieza | ICS853052 | |
| Descripción | LVPECL MULTIPLEXER | |
| Fabricantes | ICST | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS853052 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
GENERAL DESCRIPTION
ICS
The ICS853052 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer
HiPerClockS™ and a member of the HiPerClocks™family of High
Performance Clocks Solutions from ICS. The
ICS853052 has two selectable single ended
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels and translates them to 2.5V, 3.3V or 5V
LVPECL levels. The small outline 8-pin TSSOP or 8-pin SOIC
packages make this device ideal for applications where space,
high performance and low power are important.
FEATURES
• 1 differential 2.5V, 3.3V or 5V LVPECL output
• 2 selectable LVCMOS/LVTTL clock inputs
• Output frequency: TBD
• Additive phase jitter, RMS: 0.06ps (typical)
• Propagation Delay: 370ps (typical)
• 2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP58
BLOCK DIAGRAM
Da
Db
SEL
1
0
nQ
Q
PIN ASSIGNMENT
nc
Da
Db
SEL
1
2
3
4
8 VCC
7Q
6 nQ
5 VEE
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
-190
1k
Input/Output Additive Phase Jitter
@ 155.52MHz (12KHz to 20MHz)
= 0.06ps typical
10k 100k 1M
OFFSET FROM CARRIER FREQUENCY (HZ)
10M
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853052AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 1, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
101.7°C/W
1
90.5°C/W
2
89.8°C/W
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
153.3°C/W
112.7°C/W
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110
853052AG
www.icst.com/products/hiperclocks.html
11
REV. A JULY 1, 2004
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS853052.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS853052 | LVPECL MULTIPLEXER | ICST |
| ICS853052 | DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL LVPECL MULTIPLEXER |  IDT |
| ICS853054 | LVPECL/ECL CLOCK MULTIPLEXER | ICST |
| ICS853058 | LVPECL/ECL CLOCK MULTIPLEXER | ICST |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |