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PDF ICS853017 Data sheet ( Hoja de datos )
| Número de pieza | ICS853017 | |
| Descripción | LVPECL/ECL RECEIVER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
www.DataSheet4U.com
PRELIMINARY
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
GENERAL DESCRIPTION
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V dif-
ICS ferential LVPECL/ECL receiver and a member of
HiPerClockS™ the HiperclocksTM family of High Performance Clock
Solutions from ICS.The ICS853017 operates with
a positive or negative power supply at 2.5V, 3.3V or
5V, and can accept both single-ended and differential inputs. For
single-ended operation, an internally generated voltage, which is
available on output pin VBB, can be used as a switching bias volt-
age on the unused input of the differential pair. VBB can also be
used to rebias AC coupled inputs.
FEATURES
• 4 differential LVPECL / ECL 1:1 receivers
• 4 differential LVPECL clock input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 320ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V
• ECL mode operating voltage supply range:
V = 0V, V = -5.25V to -2.375V
CC EE
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100LVEL17
BLOCK DIAGRAM
D0
nD0
D1
nD1
D2
nD2
D3
nD3
VBB
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
PIN ASSIGNMENT
VCC
D0
nD0
D1
nD1
D2
nD2
D3
nD3
VBB
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 nQ0
17 Q1
16 nQ1
15 Q2
14 nQ2
13 Q3
12 nQ3
11 VEE
ICS853017
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853017AM
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol Parameter
-40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ
VOH
VOL
V
IH
VIL
VBB
VPP
VCMR
Output High Voltage; NOTE 1
-1.025
-1.005
-0.97
Output Low Voltage; NOTE 1 -1.755 -1.78 -1.765
Input High Voltage(Single-Ended)
-1.225
-1.225
-1.225
Input Low Voltage(Single-Ended)
-1.87
-1.87
-1.87
Output Voltage Reference; NOTE 2 -1.44 -1.44 -1.44
Peak-to-Peak Input Voltage
800 800 800
Input High Voltage
Common Mode Range; NOTE 3, 4
VEE+1.2V
0 VEE+1.2V
0 VEE+1.2V
IIH
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
150
150
IIL
Input
D0, D1, D2, D3
Low Current nD0, nD1,n D2, nD3
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
Max
0
150
Units
V
V
V
V
V
mV
V
µA
µA
µA
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
Symbol Parameter
-40°C
25°C
85°C
Units
Min Typ Max Min Typ Max Min Typ Max
fMAX
tPLH
tP
HL
tsk(o)
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Propagation Delay, High-to-Low; NOTE 1
Output Skew; NOTE 2, 4
>2
320
320
TBD
>2
320
320
TBD
>2
320
320
TBD
GHz
ps
ps
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
TBD
TBD
TBD
ps
tR/tF Output Rise/Fall Time 20% to 80%
175
175
175
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ps
853017AM
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 21, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
PACKAGE OUTLINE - Y SUFFIX FOR 20 LEAD SOIC
853017AM
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N 20
A -- 2.65
A1 0.10
--
A2 2.05
2.55
B 0.33 0.51
C 0.18 0.32
D
12.60
13.00
E 7.40 7.60
e 1.27 BASIC
H
10.00
10.65
h 0.25 0.75
L 0.40 1.27
α 0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
www.icst.com/products/hiperclocks.html
11
REV. A APRIL 21, 2004
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS853017.PDF ] | |
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