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Número de pieza | ICS853013 | |
Descripción | LVPECL/ECL FANOUT BUFFER | |
Fabricantes | ICST | |
Logotipo | ||
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Integrated
Circuit
Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853013 is a low skew, high perfor-
ICS mance dual 1-to-3 Differential-to-2.5V/3.3V/5V
HiPerClockS™ LVPECL/ECL Fanout Buffer and a member of
the HiperclocksTM family of High Performance
Clock Solutions from ICS. The ICS853013
operates with a positive or negative power supply at 2.5V,
3.3V, or 5V. Guaranteed output and part-to-par t skew
characteristics make the ICS853013 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• Two differential LVPECL / ECL bank outputs
• Two differential LVPECL clock input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Output skew: 40ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 570ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• LVPECL mode operating voltage supply range:
V = 2.375V to 5.25V
CC
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PCLKA
nPCLKA
PCLKB
nPCLKB
853013AM
QA0
nQA0
QA1
nQA1
QA2
nQA2
QB0
nQB0
QB1
nQB1
QB2
nQB2
PIN ASSIGNMENT
nQA0
QA0
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
VCC
nQB0
QB0
1
2
3
4
5
6
7
8
9
10
20 QA1
19 nQA1
18 QA2
17 nQA2
16 VCC
15 QB2
14 nQB2
13 QB1
12 nQB1
11 VEE
ICS853013
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 19, 2005
1 page Integrated
Circuit
Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol Parameter
-40°C
Min Typ Max
25°C
Min Typ Max
85°C
Units
Min Typ Max
VOH
VOL
VIH
VIL
VPP
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
-1.125
-1.895
-1.225
-1.87
150
-1.025 -0.92
-1.755 -1.62
-0.94
-1.535
800 1200
-1.075
-1.875
-1.225
-1.87
150
-1.005 -0.93
-1.78 -1.685
-0.94
-1.535
800 1200
-1.005
-1.86
-1.225
-1.87
150
-0.97 -0.935
-1.765 -1.67
-0.94
-1.535
800 1200
VEE+1.2V
0 VEE+1.2V
0 VEE+1.2V
0
V
V
V
V
mV
V
IIH
Input
PCLKA, PCLKB
High Current nPCLKA, nPCLKB
150 150
150 µA
IIL
Input
PCLKA, PCLKB
Low Current nPCLKA, nPCLKB
-10
-150
-10
-150
-10
-150
µA
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB
is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
Symbol Parameter
-40°C
25°C
85°C
Units
Min Typ Max Min Typ Max Min Typ Max
fMAX
tPLH
tPHL
tsk(o)
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Output Skew; NOTE 2, 4
>2
300 410
>2
510 330 425
>2 GHz
520 360 465 570 ps
300 410
510 330 425
40
520 360 465 570
40 40
ps
ps
tsk(odc) Output Duty Cycle Skew
40 40 40 ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
0.03
250
0.03
250
250
0.03
ps
ps
tR/tF Output Rise/Fall Time 20% to 80% 120 180 250 140 180
150 190
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
230
ps
853013AM
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5
REV. A OCTOBER 19, 2005
5 Page Integrated
Circuit
Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
R1 R3
250 250
2.5V
+
-
R2
62.5
R4
62.5
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
+
-
R1 R2
50 50
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
+
-
R1 R2
50 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
853013AM
www.icst.com/products/hiperclocks.html
11
REV. A OCTOBER 19, 2005
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet ICS853013.PDF ] |
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