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PDF ICS85301 Data sheet ( Hoja de datos )
| Número de pieza | ICS85301 | |
| Descripción | 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
GENERAL DESCRIPTION
The ICS85301 is a high performance 2:1 Differ-
ICS ential-to-LVPECL Multiplexer and a member of the
HiPerClockS™ HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS85301 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
FEATURES
• 2:1 LVPECL MUX
• One LVPECL output
• Two differential clock inputs can accept: LVPECL, LVDS,
CML
• Maximum input/output frequency: 3GHz
• Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
• Propagation delay: 490ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Additive phase jitter, RMS: 0.009ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK0
nPCLK0
PCLK1
nPCLK1
CLK_SEL
VBB
85301AK
0
Q
nQ
1
16 15 14 13
PCLK0 1
12 VEE
nPCLK0 2
11 Q
PCLK1 3
10 nQ
nPCLK1 4
9 VEE
5678
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
CLK_SEL
nc
VCC
1
2
3
4
5
6
7
8
16 nc
15 VEE
14 VEE
13 VCC
12 VEE
11 Q
10 nQ
9 VEE
ICS85301
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 16, 2006
1 page  
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12KHz to 20MHz)
= 0.009ps typical
10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
85301AK
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 16, 2006
5 Page 
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
R1 R3
250 250
2.5V
+
-
R2
62.5
R4
62.5
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
+
-
R1 R2
50 50
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
+
-
R1 R2
50 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
85301AK
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 16, 2006
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS85301.PDF ] | |
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