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PDF 54ACTQ374 Data sheet ( Hoja de datos )

Número de pieza 54ACTQ374
Descripción Quiet Series Octal D Flip-Flop
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! 54ACTQ374 Hoja de datos, Descripción, Manual

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August 1998
54ACQ374 54ACTQ374
Quiet Series Octal D Flip-Flop with TRI-STATE® Outputs
General Description
The ’ACQ/’ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and TRI-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered positive edge-triggered clock
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT374
n 4 kV minimum ESD immunity
n Standard Military Drawing (SMD)
— ’ACTQ374: 5962-92189
— ’ACQ374: 5962-92179
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
and Flatpak
IEEE/IEC
DS100239-1
DS100239-3
Pin Assignment for LCC
DS100239-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100239
DS100239-4
www.national.com

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54ACTQ374 pdf
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
Symbol
Parameter
VCC
TA = −55˚C to +125˚C
Units
(V) Guaranteed Limits
Conditions
ICC Maximum Quiescent
Supply Current
5.5
80.0
µA VIN = VCC
or GND (Note 11)
VOLP
VOLV
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
5.0
5.0
1.5
−1.2
V
(Notes 12, 13)
V
(Notes 12, 13)
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
Note 11: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C.
Note 12: Plastic DIP package.
Note 13: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND
Note 14: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
AC Electrical Characteristics
Symbol
Parameter
fmax
tPLH, tPHL
tPZL, tPZH
Maximum Clock
Frequency
Propagation Delay
CP to On
Output Enable Time
tPHZ, tPLZ
Output Disable Time
Note 15: Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 is 3.3V ±0.3V
VCC
(V)
(Note 15)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
54ACQ
TA = −55˚C
to +125˚C
CL = 50 pF
Min Max
95
95
1.0 16.5
1.0 11.0
1.0 16.5
1.0 11.5
1.0 12.0
1.0 10.5
Units
MHz
ns
ns
ns
Fig.
No.
AC Operating Requirements
Symbol
Parameter
ts Setup Time, HIGH or LOW
Dn to CP
th Hold Time, HIGH or LOW
Dn to CP
tw CP Pulse Width,
HIGH or LOW
Note 16: Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 is 3.3V ±0.3V
VCC
(V)
(Note 16)
3.3
5.0
3.3
5.0
3.3
5.0
54ACQ
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed
Minimum
3.0
3.0
2.0
1.5
5.0
5.0
Units
ns
ns
ns
Fig.
No.
5 www.national.com

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