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Número de pieza | S1L50000 | |
Descripción | HIGH DENSITY GATE ARRAY | |
Fabricantes | Epson | |
Logotipo | ||
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DATA SHEET
ASIC
S1L50000
S1L50000 SERIES HIGH DENSITY GATE ARRAY
DESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
• Ultra-high-speed, high density and low power consumption
• Low voltage operation: 3.3V and 2.0V
• Number of raw gates: 28,710 ~ 815,468 gates
FEATURES
• Process
0.35µm 2/3/4 layer metalization CMOS process
• Integration
A maximum of 815,468 gates (2 input NAND gate equivalent)
• Operating Speed
• I/F Levels
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
(2-input pair NAND, F/O = 2, Typical wire load)
Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(CL = 15 pF)
Input/Output TTL/CMOS/LVTTL compatible
• Input Modes
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
• Output Modes
Normal, 3-state, bi-directional, PCI
• Output Drive
• RAM
IOL = 0.1, 1, 3, 8, 12, 24 mA selectable
(Built-in level shifter is used at 5.0V)
IOL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
IOL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
Asynchronous 1-port, asynchronous 2-port
• Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer: Built-in interfaces of both high and low voltages possible
• Operation possible at VDD = 2.0 ± 0.2V
i i i iEPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
1
1 page DATA SHEET
ASIC
S1L50000
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol Min Typ
Max
Power Supply Voltage (High Voltage)
HVDD
4.75 5.00
4.50 5.00
5.25
5.50
Power Supply Voltage (Low Voltage)
Input Voltage
Ambient Temperature
LVDD
HVI
LVI
Ta
3.00
VSS
VSS
0
-40
3.30
--
--
25
25
3.60
HVDD
LVDD*1
70*2
85*3
Normal Input for Rising Edge Input
tri
-- --
50
Normal Input for Falling Edge Input
tri
-- --
50
Schmitt Input for Rising Edge Input
tri
-- --
5
Schmitt Input for Falling Edge Input
tri
-- --
5
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
Unit
V
V
V
°C
ns
ns
ms
ms
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol Min Typ
Max Unit
Power Supply Voltage (High Voltage)
Power Supply Voltage (Low Voltage)
Input Voltage
Ambient Temperature
HVDD
LVDD
HVI
LVI
Ta
3.00
1.80
VSS
VSS
0
-40
3.30
2.00
--
--
25
25
3.60
2.20
HVDD
LVDD
70*1
85*2
V
V
V
°C
Normal Input for Rising Edge Input
Htri
-- -- 50 ns
Ltri
-- --
100
Normal Input for Falling Edge Input
Htfi
-- -- 50 ns
Ltfi
-- --
100
Schmitt Input for Rising Edge Input
Htri
-- --
5
ms
Ltri
-- --
10
Schmitt Input for Falling Edge Input
Htfi
-- --
5
ms
Ltfi
-- --
10
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems or HIDC and
HIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
i i i iEPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
5
5 Page DATA SHEET
EDA/CAE SUPPORT (continued)
• Static Timing
Synopsys: PrimeTime (DesignTime)
Viewlogic (Synopsys): Motive
• Layout Verification
Cadence: Dracula/LVS
ASIC
S1L50000
i i i iEPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet S1L50000.PDF ] |
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