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PDF M63160J Data sheet ( Hoja de datos )

Número de pieza M63160J
Descripción STEPPING MOTOR DRIVER
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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M63160J
STEPPING MOTOR DRIVER
REJ03F0038-0110Z
Rev.1.1
May.21.2004
Description
This semiconductor integrated circuit includes for H bridge circuit for stepper Motor drive.Output transistor is DMOS.
Motor power supply;is possible to drive until 52V maximum.
Function Outline
1. Maximum output current : Peak 2.0A
2. Low output ’s Ron.: 1.1
3. Includes two stepping motor driver circuit
* Two DC Motor and One Stepping Motor possible to drive.
4. Motor control by serial interface.(Frequency=20MHz maximum)
5. Includes 5V- switching regulator.
6. Includes thermal shut down circuit
PIN CONFIGURATION
PIN CONFIGURATION(TOP VIW)
44 PIN PLCC
STB12 29
DATA12 30
EN1 31
CTL1 32
CTL2 33
Ground 34
Ground 35
CTL34 36
EN2 37
DATA34 38
STB34 39
17 NC
16 Reset
15 EXCLK
14 (Tmon)
13 Vout
12 Ground
11 Ground
10 FB
9 Vboot
8 CP2
7 CP1
Outline 44 PIN PLCC
Rev.1.1, May.21.2004, page 1 of 17

1 page




M63160J pdf
M63160J
Electrical Characteristics
SYMBOL PARAMETER
Common Block
ICC-L
Vcc standby current
IM-L Motor stop current
Vboot
Bootstrap voltage
Fcp1
Bootstrap frequency
Lvoldl
Regulator voltage
detector
LvoldH
Regulator voltage
detector
Vhys
Vhys
Tmon
Tmon Voltage
[Power Block]
Ron1
Output RDS(ON)
Ron2
Output RDS(ON)
[Logic Input Terminal]
VinH
Serial port input voltage
High
VinL
Serial port input voltage
Low
IinH Serial port input current
High
IinL Serial port input current
Low
[Serial port]
fsclk
Serial port clock
frequency
tset Serial port setup time
thold
Serial port hold time
[Switching regulator]
REGout1
5V regulator output
voltage1
Fclk-Reg Clock frequency
Rds(on)-
Reg
Sw.Reg.-ON
Sfts Soft Start
Climit
Output Limits Voltage
Climit
Iout
EFFI1
EFFI2
Cut of FB Voltage
REG Output Current
Efficiency
(Design Value)
Efficiency
(Design Value)
CONDITIONS
VCC=5V, Circuit current
of Motor stopping
VP=42V, Circuit current
of Motor stopping
The case of supply
voltage decreasing
The case of supply
voltage increasing
Ta=25°C
Total of top and bottom
(Ta=25°C)
Total of top and bottom
(Ta=25°C)
V force:5V
V force:0V
CLK12, CLK34
Load current :300mA
VP voltage :10V to 47V
Load current : 600mA
to 1.2A
VP=42V L=330uH
C=470µF Iout=300mA
VP=15 VL=330uH
C=470µF Iout=300mA
(Ta=25°C, VP=42V unless otherwise noted)
LIMITS
MINIMUM TYPCAL MAXMUM UNIT
— 5.5 7
mA
150
4.18
180
710
6.0
52.6
200
LvoldH
-Vhys
4.4
200
740
7.5
61.2
250
4.62
220
770
mA
V
kHz
V
V
mV
mV
— 1.1 1.4
— 1.1 1.4
2 — REGout V
0 — 0.8 V
50 100 200 µA
-10 0
+10 µA
— — 20 MHz
12.5 — — nS
10 — — nS
4.75 5.00 5.25 V
75 100 125 kHz
— 0.7 —
5 10 15 ms
— 4.75 V
0.8 1.2 1.5 A
— 300 500 mA
— 70 — %
— 80 — %
Rev.1.1, May.21.2004, page 5 of 17

5 Page





M63160J arduino
M63160J
A motor control logic condition and explanation
1, Data setup
1-1, Data taking in: CLK rising edge
1-2, Data input 1: It carries out in order of D15 - >D0.
1-3, Data input 2: A Mode setup is performed after initial setting.
1-4, Every 16 bits, it is a STB signal and it is Closed.
1-5, A data setup of Ch2 For Test is not performed.
1-6, Sync.Rect.Control “Active” At the time of a setup, The inside of Fast Decay performs negative voltage
detection. FET is set to all OFF when current flows in the right direction.
2, RESET terminal
Low: All data reset(All FET OFF)High :Data setup Standby state
When a RESET terminal is set to “L” and a Motor drive is performed, A REST terminal is set to “H” and serial data
is re inputted.
Internal logic reset is Logic composition of a RESET terminal and a Low Voltage detection machine is performed.
When rapid high load is in FB, a Low Voltage detection machine outputs “L”, Internal logic is reset when an output
does not return to less than 1 µs at “H.”
RESET terminal “L” Internal logic will be in an initial state.(All FET serves as all OFF )
A S/W- REG part continues operation.
3, EN terminal
Low: External PWM Mode Slow Decay or Fast Decay
Off Time Fast Decay Time: Sleep
A current detection condition setup at the time of Decay is performed by Sync.Rect.Control Active or Passive.
However, current detection is effective only at the time of Fast Decay.(Slow is invalid.)
High :Internal PWM Mode Motor drive state FET ON- >OFF - >ON
4, Motor drive
Motor drive :RESET terminal “H” EN terminal “H” It drives after a Mode Data setup.
Motor STOP :RESET terminal “L” is STOP.
RESET terminal “H” EN terminal “L”: It is set to Decay by External PWM Mode. All FETOFF comes after setting
current detection.
EN is not related to “L or H” in early stages. It FET all turns off till control logic initial setting and the completion
of a Mode setting. EN is always after control logic initial setting and the completion of a Mode setting at “L.”, If it
is External PWM Slow Decay Mode, it is Start about Slow Decay.
(It FET all turns off at the time of Fast Decay Mode.)
After control logic initial setting and the completion of a Mode setting, FET is set to being turned on by EN “H”
and it is compulsorily set to Decay Mode by EN “L.”
However, even if a setup of External PWM Slow Decay Mode is EN “L”, it is reflected.
5, Current detection by Decay
The conditions which perform current detection by Decay
Internal PWM: Sync.Rect.EnableControl1 “H”, Inside of Fast Decay in Mixed Decay Mode
External PWM: Sync.Rect.EnableControl1 “H”, Fast Decay Mode
In addition, Decay current detection is not performed on conditions.
Internal PWM: It changes to Decay from FET ON by the current detection COM., Fast Decay Time-OffTime starts
in this stage. It is Start about the current detection in Decay, Fast Decay Time as a trigger. Detection is stopped after
Fast Decay Time completion.
When setting Decay current is detected during Fast Decay time, FET is all turned off only within Fast Decay time.
It is referred to as Slow Decay till OFF Time completion after Fast Decay completion.
External PWM: With EN terminal “L”, it goes into Regeneration Mode compulsorily. Decay current detection is
Started to a trigger for the signal of EN “L.” Detection is continued until the reversal signal from COM comes out.
Decay current detection serves as [EN] STOP by “H”, and FET is turned on
Rev.1.1, May.21.2004, page 11 of 17

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