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PDF VT8363A Data sheet ( Hoja de datos )

Número de pieza VT8363A
Descripción KT133A AMD ATHLON NORTH BRIDGE
Fabricantes VIA 
Logotipo VIA Logotipo



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VT8363A pdf
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KT133A - VT8363A
LIST OF FIGURES
FIGURE 1. KT133A SYSTEM BLOCK DIAGRAM USING THE VT82C686A SOUTH BRIDGE........................................ 4
FIGURE 2. VT8363A KT133A BALL DIAGRAM (TOP VIEW) ................................................................................................ 6
FIGURE 3. CPU / SDRAM / AGP / PCI CLOCK CONNECTIONS ......................................................................................... 15
FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 34
FIGURE 5. MECHANICAL SPECIFICATIONS - 552-PIN BALL GRID ARRAY PACKAGE ........................................... 48
Preliminary Revision 0.1, October 9, 2000
-iii-
List of Figures

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VT8363A arduino
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KT133A - VT8363A
Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported
such as snoop ahead, snoop filtering, L1/L2 write-back forward to PCI master, and L1/L2 write-back merged with PCI post write
buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also
implemented for further improvement of overall system performance.
The 352-pin Ball Grid Array VT82C686A PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C686A also includes an
integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33/66 for
33/66 MB/sec transfer rate, integrated USB interface with root hub and four function ports with built-in physical layer transceivers,
Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface. The
VT82C686A also includes an AC97 / MC97 link for interface to external audio and modem codecs, and all “Super-I/O” functions
(serial ports, parallel port, and floppy drive interface and game port).
For sophisticated power management, KT133A provides independent clock stop control for the CPU / SDRAM, PCI, and AGP
buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the
SDRAM control signals for Suspend-to-DRAM operation. The VT82C686A also includes a complete hardware monitoring
subsystem for monitoring and control of internal and external (motherboard and system) conditions including voltages,
temperatures, fan speeds, switch open/close states, etc. Coupled with the VT82C686A south bridge chip, a complete power
conscious PC main board can be implemented with no external TTLs.
The KT133A chipset is ideal for high performance, high quality, high energy efficient and high integration desktop AGP / PCI /
ISA computer systems.
Preliminary Revision 0.1, October 9, 2000
-5-
Overview

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