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PDF SC1486A Data sheet ( Hoja de datos )
| Número de pieza | SC1486A | |
| Descripción | Dual Synchronous Buck DDR and DDR2 Power Supply Controller | |
| Fabricantes | Semtech Corporation | |
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SC1486A
Dual Synchronous Buck
DDR and DDR2 Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC1486A is a dual output constant on-time
synchronous buck PWM controller optimized for cost
effective mobile DDR and DDR2 applications. Features
include high efficiency, a fast dynamic response with no
minimum on time, a REFIN input and a buffered REFOUT
pin capable of sourcing 3mA. The excellent transient
response means that SC1486A based solutions will
require less output capacitance than competing fixed
frequency converters.
The output voltage of the first controller can be adjusted
from 0.5V to VCCA. In DDR applications, this voltage is
set to 2.5 volts, and in DDR2, 1.8V. A resistor divider
from this supply is used to drive the REFIN pin of the
second controller. A unity gain buffer drives the REFOUT
pin to the same potential as REFIN. The second controller
regulates its output to REFOUT. Two frequency setting
resistors set the on-time for each buck controller. The
frequency can thus be tailored to minimize crosstalk. The
integrated gate drivers feature adaptive shoot-through
protection and soft switching, requiring no gate resistors
for the top MOSFET. Additional features include cycle-
by-cycle current limit, digital soft-start, over-voltage and
under-voltage protection, and a Power Good output for
each controller.
Typical Application Circuit
1% DC accuracy
Compatible with DDR & DDR2 memory power
requirements
Constant on-time for fast dynamic response
VIN range = 1.8V – 25V
DC current sense using low-side RDS(ON) sensing
or sense resistor
Integrated reference buffer for VTT
Low power S3 state with high-Z VTT
Resistor programmable on-time
Cycle-by-cycle current limit
Digital soft-start
PSAVE option for VDDQ
Over-voltage/under-voltage fault protection
<20µA shutdown current
Low quiescent power dissipation
Two Power Good indicators
Separate enable for each switcher
Integrated gate drivers with soft switching - no gate
resistors required
Efficiency >90%
28 Lead TSSOP (lead free available)
Applications
Notebook computers
CPU I/O supplies
Handheld terminals and PDAs
VBAT
5VSUS
5VSUS
VBAT
R1
RTON1
R5
PGOOD
C5
1nF
VBAT 5VSUS VDDQ
R2
10R
VDDQ
R3
R7
C6
1uF
VSSA1
5VSUS
U1
22
EN/PSV1
23
TON1
24
VOUT1
25
VCCA1
26
FB1
27
PGD1
28
VSSA1
SC1486A
7
BST1
6
DH1
5
LX1
4
ILIM1
3
VDDP1
2
DL1
1
PGND1
D1
C1 0.1uF
R4
C4
1uF
5VRUN
R10
RTON2
PGOOD
Revision: June 22, 2004
C11
1nF
R8 R9
10k 10R
R11
C12
100nF
REFOUT
R12
10R
VTT
R15
10k
C13
1uF
C14
1uF
VSSA2
8
REFIN
9
TON2
10
REFOUT
11
VCCA2
12
FB2
13
PGD2
14
VSSA2
21
BST2
20
DH2
19
LX2
18
ILIM2
17
VDDP2
16
DL2
15
PGND2
1
D2
C7 0.1uF
R13
C10
1uF
Q1 C2
10uF
L1
VDDQ
C3
+
Q2 R6 0R
VSSA1
VBAT
Q3 C8
10uF
L2
VTT
C9
+
Q4 R14 0R
VSSA2
www.semtech.com
1 page  
SC1486A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions
25°C
-40°C to 125°C Units
Min Typ Max Min Max
Gate Drivers
Shoot-Through Delay (4)
DH or DL rising
30
ns
DL Pull-Down Resistance
DL Sink Current
DL Pull-Up Resistance
DL Source Current
DL low
DL = 2.5V
DL high
DL = 2.5V
0.8
3.1
2
1.3
1.6 Ω
Α
4Ω
A
DH Pull-Down Resistance
DH Pull-Up Resistance
DH Sink/Source Current
DH low, BST - LX = 5V
DH high, BST - LX = 5V
DL = 2.5V
2
2
1.3
4Ω
4Ω
A
Notes:
(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the
ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the
low-side MOSFET.
(3) clks = switching cycles.
(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below.
(5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
(6) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Shoot-Through Delay Timing Diagram
LX
DH
DL
tplhDL
DL
tplhDH
2004 Semtech Corp.
5
www.semtech.com
5 Page 
SC1486A
POWER MANAGEMENT
Application Information (Cont.)
Current Limit Circuit (Cont.)
latches off due to output overvoltage (see Output
Overvoltage Protection).
Power Good Output
Each controller has its own power good output. Power
good is an open-drain output and requires a pull-up
resistor. When the output voltage is 10% above or below
its set voltage, PGD gets pulled low. It is held low until
the output voltage returns to within 10% of the output
set voltage. PGD is also held low during start-up and will
not be allowed to transition high until soft start is over
(440 switching cycles) and the output reaches 90% of
its set voltage. There is a 5µs delay built into the PGD
circuitry to prevent false transitions.
Output Overvoltage Protection
When the output exceeds 10% of the its set voltage the
low-side MOSFET is latched on. It stays latched on and
the controller is latched off until reset (see below). There
is a 5µs delay built into the OV protection circuit to
prevent false transitions. An OV fault in either controller
will not cause the other one to shutdown. Note: to reset
VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled.
To reset VTT from a fault, VCCA2 or REFIN must be
toggled.
Output Undervoltage Protection
When the output is 30% below its set voltage the output
is latched in a tri-stated condition. It stays latched and
the controller is latched off until reset (see below). There
is a 5µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in either controller
will not cause the other one to shutdown. Note: to reset
VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled.
To reset VTT from a fault, VCCA2 or REFIN must be
toggled.
POR, UVLO and Softstart
An internal power-on reset (POR) occurs when VCCA1 and
VCCA2 exceed 3V, resetting the fault latch and soft-start
counter, and preparing the PWM for switching. VCCA
undervoltage lockout (UVLO) circuitry inhibits switching
and forces the DL gate driver high until VCCA rises above
4.2V. At this time the circuit will come out of UVLO and
begin switching, and with the softstart circuit enabled,
will progressively limit the output current (by limiting the
current out of the ILIM pin) over a predetermined time
period of 440 switching cycles.
The ramp occurs in four steps:
1) 110 cycles at 25% ILIM with double minimum off-time
2) 110 cycles at 50% ILIM with normal minimum off-time
3) 110 cycles at 75% ILIM with normal minimum off-time
4) 110 cycles at 100% ILIM with normal minimum
off-time. At this point the output undervoltage and power
good circuitry is enabled.
There is 100mV of hysteresis built into the UVLO circuit
and when VCCA falls to 4.1V (nom.) the output drivers
are shut down and tristated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (below ~1V). Conversely, it
monitors the phase node, LX, to determine the state of
the high side MOSFET, and prevents the low-side MOSFET
from turning on until DH is fully off (LX below ~1V). Be
sure there is low resistance and low inductance between
the DH and DL outputs to the gate of each MOSFET.
DDR Reference Buffer
The reference buffer is capable of driving 3mA and sinking
25µA. Since the output is class A, if additional sinking is
required an external pulldown resistor can be added.
Make sure that the ground side of this pulldown is tied
to VSSA2. As with most opamps, a small resistor is
required when driving a capacitive load. To ensure stability
use either a 10Ω resistor in series with a 1µF capacitor
or a 100Ω resistor in series with a 0.1µF capacitor from
REFOUT to AGND2.
Since it is possible to have as much as 10µF to 20µF of
capacitance at the memory socket or on-board the
DIMMs, it is recommended that a 0Ω resistor is placed
between REFOUT and the DIMM sockets. This allows the
addition of extra resistance between REFOUT and the
DIMMs to avoid spurious OVP at startup, which can occur
if REFOUT rises really slowly and VTT overshoots it. The
extra resistance allows REFOUT to rise faster, avoiding
this issue.
REFIN should also be filtered so that VDDQ ripple does
not appear at the REFIN pin. If a resistor divider is used
to create REFIN from VDDQ, then a 0.1µF capacitor from
REFIN to VSSA2 will provide adequate filtering.
2004 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet SC1486A.PDF ] | |
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