|
|
PDF IDT71V67703 Data sheet ( Hoja de datos )
| Número de pieza | IDT71V67703 | |
| Descripción | (IDT71V67703 / IDT71V67903) Burst Counter Flow-Through Outputs / Single Cycle Deselect | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT71V67703 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
256K X 36, 512K X 18
IDT71V67703
3.3VSynchronousSRAMs
IDT71V67903
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
Features
x 256K x 36, 512K x 18 memory configurations
x Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 3.3V I/O supply (VDDQ)
x Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
Description
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
data, address and control registers. There are no registers in the data
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67703/7903 can provide four cycles of
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE Chip Enable
CS0, CS1
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67903.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5309 tbl 01
©2002 Integrated Device Technology, Inc.
1
DECEMBER 2003
DSC-5309/05
1 page  
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
5309 drw 02a
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.452
5 Page 
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table (1, 2)
Operation
GW BWE BW1 BW2 BW3 BW4
Read
HHX X X X
Read
HL HHHH
Write all Bytes
LXXXXX
Write all Bytes
HL L L L L
Write Byte 1(3)
HL L HHH
Write Byte 2(3)
HL HL HH
Write Byte 3(3)
HL HHL H
Write Byte 4(3)
HL HHHL
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67903.
3. Multiple bytes may be selected during the same cycle.
5309 tbl 12
Asynchronous Truth Table (1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
LL
Data Out
Active
Read H L
High-Z
Active
Write
XL
High-Z – Data In
Active
Deselected
XL
High-Z
Standby
Sleep Mode
XH
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
High-Z
Sleep
5309 tbl 13
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address
000 110 11
Second Address
0 100 1110
Third Address
10 11000 1
Fourth Address(1)
11100 100
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
5309 tbl 14
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
A1 A0 A1 A0
First Address
000 1
Second Address
0 110
Third Address
10 11
Fourth Address(1)
1 10 0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 3
A1 A0
10
11
00
01
Sequence 4
A1 A0
11
00
01
10
5309 tbl 15
6.1412
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet IDT71V67703.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT71V67702 | (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect | IDT |
| IDT71V67703 | (IDT71V67703 / IDT71V67903) Burst Counter Flow-Through Outputs / Single Cycle Deselect | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |