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PDF ADC08D1500 Data sheet ( Hoja de datos )
| Número de pieza | ADC08D1500 | |
| Descripción | A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
June 2005
ADC08D1500
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D
Converter
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC08D1500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.7 GSPS. Consuming
a typical 1.9 Watts at 1.5 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.25 ENOB with a 748 MHz input signal
and a 1.5 GHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS digital out-
puts are compliant with IEEE 1596.3-1996, with the excep-
tion of an adjustable common mode voltage between 0.8V
and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C ≤ TA ≤ +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n Interleave Mode for 2x Sampling Rate
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 748 MHz Input
n DNL
n Power Consumption
— Operating
— Power Down Mode
8 Bits
1.5 GSPS (min)
10-18 (typ)
7.25 Bits (typ)
±0.15 LSB (typ)
1.9 W (typ)
3.5 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
© 2005 National Semiconductor Corporation DS201521
20152153
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
83 / 78 DI7− / DQ7−
84 / 77 DI7+ / DQ7+
85 / 76 DI6− / DQ6−
86 / 75 DI6+ / DQ6+
89 / 72 DI5− / DQ5−
90 / 71 DI5+ / DQ5+
91 / 70 DI4− / DQ4−
92 / 69 DI4+ / DQ4+
93 / 68 DI3− / DQ3−
94 / 67 DI3+ / DQ3+
95 / 66 DI2− / DQ2−
96 / 65 DI2+ / DQ2+
100 / 61 DI1− / DQ1−
101 / 60 DI1+ / DQ1+
102 / 59 DI0− / DQ0−
103 / 58 DI0+ / DQ0+
104 / 57 DId7− / DQd7−
105 / 56 DId7+ / DQd7+
106 / 55 DId6− / DQd6−
107 / 54 DId6+ / DQd6+
111 / 50 DId5− / DQd5−
112 / 49 DId5+ / DQd5+
113 / 48 DId4− / DQd4−
114 / 47 DId4+ / DQd4+
115 / 46 DId3− / DQd3−
116 / 45 DId3+ / DQd3+
117 / 44 DId2− / DQd2−
118 / 43 DId2+ / DQd2+
122 / 39 DId1− / DQd1−
123 / 38 DId1+ / DQd1+
124 / 37 DId0− / DQd0−
125 / 36 DId0+ / DQd0+
Equivalent Circuit
Description
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100Ω
differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should always be terminated with a
100Ω differential resistor.
79 OR+
80 OR-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range ±325 mV or ±435 mV as defined by the FSR pin).
82 DCLK+
81 DCLK-
2, 5, 8,
13, 16,
17, 20,
25, 28,
33, 128
VA
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode.
Analog power supply pins. Bypass these pins to ground.
5 www.national.com
5 Page 
Converter Electrical Characteristics (Continued)
NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.
The specifications in this section cannot be guaranteed until device characterization has taken place. The following
specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1.5 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-
Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
fCLK1
Maximum Input Clock
Frequency
Normal Mode (non DES) or DES
1.7 1.5 GHz (min)
Mode
fCLK2
Minimum Input Clock
Frequency
Normal Mode (non DES)
200
MHz
fCLK2
Minimum Input Clock
Frequency
DES Mode
500 MHz
Input Clock Duty Cycle
200 MHz ≤ Input clock frequency ≤
1.5 GHz (Normal Mode) (Note 12)
50
20 % (min)
80 % (max)
Input Clock Duty Cycle
500MHz ≤ Input clock frequency ≤
1.5 GHz (DES Mode) (Note 12)
50
20 % (min)
80 % (max)
tCL Input Clock Low Time
tCH Input Clock High Time
DCLK Duty Cycle
(Note 11)
(Note 11)
(Note 11)
333 133 ps (min)
333 133 ps (min)
45 % (min)
50
55 % (max)
tRS
tRH
tSD
tRPW
Reset Setup Time
Reset Hold Time
Syncronizing Edge to DCLK
Output Delay
Reset Pulse Width
(Note 11)
(Note 11)
fCLKIN = 1.5 GHz
fCLKIN = 200 MHz
(Note 11)
150
250
3.53
3.85
ps
ps
ns
Clock Cycles
4
(min)
Differential Low to High
tLHT Transition Time
10% to 90%, CL = 2.5 pF
250
ps
Differential High to Low
tHLT Transition Time
10% to 90%, CL = 2.5 pF
250
ps
50% of DCLK transition to 50% of
tOSK
DCLK to Data Output Skew
Data transition, SDR Mode
±50
and DDR Mode, 0˚ DCLK (Note 11)
ps (max)
tSU
Data to DCLK Set-Up Time
DDR Mode, 90˚ DCLK (Note 11)
667
tH
DCLK to Data Hold Time
DDR Mode, 90˚ DCLK (Note 11)
667
Input CLK+ Fall to Acquisition of
tAD
Sampling (Aperture) Delay
Data
1.3
ps
ps
ns
tAJ Aperture Jitter
0.4
Input Clock to Data Output
50% of Input Clock transition to 50%
tOD
Delay (in addition to Pipeline
of Data transition
3.1
Delay)
ps rms
ns
DI Outputs
13
DId Outputs
14
Pipeline Delay (Latency)
(Notes 11, 14)
DQ Outputs
Normal Mode
DES Mode
13
13.5
Input Clock
Cycles
DQd Outputs
Normal Mode
DES Mode
14
14.5
Over Range Recovery Time
Differential VIN step from ±1.2V to
0V to get accurate conversion
1
Input Clock
Cycle
11 www.national.com
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| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet ADC08D1500.PDF ] | |
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