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Dallas - Power Monitor Chip

Numéro de référence DS1231
Description Power Monitor Chip
Fabricant Dallas 
Logo Dallas 





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DS1231 fiche technique
DS1231/S
DS1231/S
Power Monitor Chip
FEATURES
Warns processor of an impending power failure
Provides time for an orderly shutdown
Prevents processor from destroying nonvolatile
memory during power transients
Automatically restarts processor after power is
restored
Suitable for linear or switching power supplies
Adjusts to hold time of the power supply
Supplies necessary signals for processor interface
Accurate 5% or 10% VCC monitoring
Replaces power-up reset circuitry
No external capacitors required
Optional 16-pin SOIC surface mount package
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise tem-
perature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a pro-
cessor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high volt-
age inputs to the power supply regulators. If line isola-
tion is required a UL-approved opto-isolator can be di-
rectly interfaced to the DS1231. The time for processor
PIN ASSIGNMENT
IN
MODE
TOL
GND
1
2
3
4
8 VCC
7 NMI
6 RST
5 RST
DS1231 8–Pin DIP
(300 MIL)
See Mech. Drawings
Section
NC 1 16 NC
IN 2 15 VCC
NC 3 14 NC
MODE 4 13 NMI
NC 5 12 NC
TOL 6 11 RST
NC 7 10 NC
GND
8
9 RST
DS1231S 16–Pin SOIC
(300 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN – Input
MODE
– Selects input pin characteristics
TOL
GND
– Selects 5% or 10% VCC detect
– Ground
RST
– Reset (Active High)
RST
– Reset (Active Low, open drain)
NMI – Non–Maskable Interrupt
VCC – +5V Supply
NC – No Connections
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor uncondi-
tionally halts the processor to prevent spurious cycles
by enabling Reset as VCC falls below a selectable 5 or
10 percent threshold. When power returns, the proces-
sor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.
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