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PDF ICS84320-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS84320-01 | |
| Descripción | CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
ICS
The ICS84320-01 is a general purpose, dual out-
put Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™ quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS84320-01 has a se-
lectable TEST_CLK or crystal inputs. The VCO operates at a
frequency range of 620MHz to 780MHz. The VCO frequency
is programmed in steps equal to the value of the input refer-
ence or crystal frequency. The VCO and output frequency
can be programmed using the serial or parallel interfaces to
the configuration logic. The low phase noise characteristics
of the ICS84320-01 make it an ideal clock source for 10 Gigabit
Ethernet, SONET, and Serial Attached SCSI applications.
FEATURES
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 77.5MHz to 780MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
• Parallel or serial interface for programming counter
and output dividers
• Duty cycle: 49% - 51% (N > 1)
• RMS period jitter: 2.0ps (typical)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12KHz to 20MHz): 2.5ps (typical)
Phase noise: 155.52MHz (typical), using a 38.88MHz crystal
Offset
Noise Power
100Hz .................. -90.5 dBc/Hz
1KHz ................ -114.2 dBc/Hz
10KHz ................ -123.6 dBc/Hz
100KHz ................ -128.1 dBc/Hz
• 3.3V supply voltage
• Lead-Free/Annealed package available
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
OSC
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
VCO
÷M
÷N
÷1
0 ÷2
÷4
1 ÷8
CONFIGURATION
INTERFACE
LOGIC
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
nc 7
ICS84320-01
24 XTAL2
23 TEST_CLK
22 XTAL_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
VEE 8
17 MR
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
84320AY-01
www.icst.com/products/hiperclocks.html
REV. A AUGUST 24, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5 V
Outputs, VO (LVCMOS)
Outputs, I (LVPECL)
O
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, TSTG
-0.5V to VDDO + 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE
4A.
POWER
SUPPLY
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC
VCCA
VCCO
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.135
3.135
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
22
Units
V
V
V
mA
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical
VCO_SEL, XTAL_SEL, MR,
VIH
Input
S_LOAD, nP_LOAD, N0:N1,
High Voltage S_DATA, S_CLOCK, M0:M8
TEST_CLK
2
2
VCO_SEL, XTAL_SEL, MR,
VIL
Input
S_LOAD, nP_LOAD, N0:N1,
Low Voltage S_DATA, S_CLOCK, M0:M8
TEST_CLK
-0.3
-0.3
M0-M4, M6-M8, N0, N1, MR,
IIH
Input
High Current
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
VCC = 3.465V,
IIL
Input
S_DATA, S_LOAD, nP_LOAD
Low Current
M5, XTAL_SEL, VCO_SEL
VIN = 0V
VCC = 3.465V,
VIN = 0V
-5
-150
VOH
Output
High Voltage
TEST; NOTE 1
2.6
Maximum
VCC + 0.3
VCC + 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
VOL
Output
Low Voltage
TEST; NOTE 1
NOTE
1:
Outputs
terminated
with
50Ω
to
V /2.
CCO
84320AY-01
www.icst.com/products/hiperclocks.html
0.5 V
REV. A AUGUST 24, 2004
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS84320-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have the
same length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL1) and 24 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C1
U1
PIN 1
X1
C2
C11
R7
C16
VCCA
GND
VCC
VIA
Close to the input
pins of the
receiver
84320AY-01
C15
C14
TL1 R1
R2
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
R3
R4
FIGURE 5B. PCB BOARD LAYOUT FOR ICS84320-01
www.icst.com/products/hiperclocks.html
11
REV. A AUGUST 24, 2004
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS84320-01.PDF ] | |
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