PDF MAX3875A Data sheet ( Hoja de datos )

Número de pieza	MAX3875A
Descripción	Clock Recovery and Data Retiming IC
Fabricantes	Maxim Integrated Products
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No Preview Available ! www.DataSheet4U.com 19-2362; Rev 1; 3/02 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC General Description The MAX3875A is a compact, low-power clock recov- ery and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. Differential PECL-compatible outputs are provid- ed for both clock and data signals, and an additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL- compatible loss-of-lock (LOL) monitor. The MAX3875A is designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Its jitter performance exceeds all of the SONET/SDH specifications. This device operates from a single +3.3V to +5.0V supply over a -40°C to +85°C temperature range. The typical power consumption is only 400mW with a +3.3V supply. It is available in a 32-pin TQFP package, as well as in die form. Applications SDH/SONET Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects 2.488Gbps ATM Receiver Digital Video Transmission SDH/SONET Test Equipment Features o Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications o 400mW Power Dissipation (at +3.3V) o Clock Jitter Generation: 0.003UIRMS o Single +3.3V or +5V Power Supply o Fully Integrated Clock Recovery and Data Retiming o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o Tolerates >2000 Consecutive Identical Digits o Loss-of-Lock Indicator o Differential PECL-Compatible Data and Clock Outputs Ordering Information PART MAX3875AEHJ MAX3875AE/D TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 32 TQFP Dice* * Dice are designed to operate over this range, but are tested and guaranteed at TA = +25°C only. Contact factory for availability. Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V PHOTO- DIODE VCC 0.01µF 0.01µF MAX3866 OUT+ IN PRE/POSTAMPLIFIER LOP OUT- TTL +3.3V TTL VCC PHADJ+ PHADJ- LOL SDO+ SDI+ SDO- SDI- MAX3875A SLBI- SLBI+ SIS FIL+ SCLKO+ SCLKO- FIL- +3.3V 130Ω 130Ω +3.3V 82Ω 82Ω +3.3V MAX3885 130Ω 130Ω 1:16 DESERIALIZER 82Ω 82Ω SYSTEM LOOPBACK TTL 1µF ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Pin Description (continued) PIN NAME FUNCTION 19 SCLKO+ Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+. 22 SDO- Negative Data Output, PECL compatible, 2.488Gbps 23 SDO+ Positive Data Output, PECL compatible, 2.488Gbps 25 LOL Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor) 27 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 28 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 30 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 31 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. SIS PHADJ+ PHADJ- FIL+ FIL- SDI+ SDI- SLBI+ SLBI- AMP MUX AMP MAX3875A PHASE AND FREQUENCY DETECTOR LOOP FILTER DQ CK I VCO Q SDO+ SDO- CML SCLKO+ SCLKO- CML LOL TTL Figure 3. Functional Diagram Detailed Description The MAX3875A consists of a fully integrated phase- locked loop (PLL), input amplifier, data retiming block, and PECL output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. Input Amplifier Input amplifiers are implemented for both the main data and system loopback inputs. These amplifiers accept a differential input amplitude from 50mVP-P up to 800mVP-P. The bit error rate is better than 1 x 10-10 for input signals as small as 10mVp-p, although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. Phase Detector The phase detector incorporated in the MAX3875A pro- duces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. _______________________________________________________________________________________ 5 5 Page

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