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PDF FMS6501 Data sheet ( Hoja de datos )
| Número de pieza | FMS6501 | |
| Descripción | 12 Input 9 Output Video Switch Matrix | |
| Fabricantes | Fairchild Semiconductor | |
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May 2005
FMS6501
12 Input 9 Output Video Switch Matrix with Input Clamp,
Input Bias Circuitry, and Output Drivers
Features
■ 12 x 9 Crosspoint Matrix
■ Supports SD, PS, and HD 1080i/1080p Video
■ Input Clamp / Bias Circuitry
■ AC or DC-Coupled Inputs
■ AC or DC-Coupled Outputs
■ Dual Load(75Ω) Output Drivers with High Impedance Disable
■ One-to-One or One-to-Many Input to Output Switching
■ Programmable Gain: +6, +7, +8 or +9dB
■ I2CTM Compatible Digital Interface, Standard Mode
■ 3.3V or 5V single supply operation
■ Lead (Pb) Free SSOP-28 Package
Applications
■ Cable and Satellite set top boxes
■ TV and HDTV Sets
■ A/V Switchers
■ Personal Video Recorders (PVR)
■ Security / Surveillance
■ Video Distribution
■ Automotive (In-Cabin Entertainment)
Description
The FMS6501 provides 12 inputs which can be routed to any of
9 outputs. Each input can be routed to one or more outputs but
only one input may be routed to any output. The input to output
routing is controlled via an I2C compatible digital interface.
Each input supports an integrated clamp option to set the output
sync tip level of video with sync to ~300mV. Alternatively, the
input may be internally biased to center signals without sync
(Chroma, Pb, Pr) at ~1.25V. These DC output levels are for the
6dB gain setting. Higher gain settings will increase the DC out-
put levels accordingly. The input clamp / bias mode is selected
via I2C.
Unused outputs may be powered down to reduce power dissi-
pation.
Block Diagram
IN1 C / B
IN2 C / B
IN12
SDA
SCL
ADDR
VCC (2)
GND (2)
C/B
OUT1
OUT2
©2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1A
1
Programmable
Gain
6, 7, 8 or 9dB
OUT9
Programmable
Enable/Disable
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
Tc = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with
0.1uF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220uF into 150Ω
loads, referenced to 400kHz; unless otherwise noted.
Symbol
ICC
VOUT
ROFF
Vclamp
Vbias
PSRR
Parameter
Supply Current1
Video Output Range
Off Channel Output Impedance
DC Output Level1
DC Output Level1
Power Supply Rejection Ratio
Conditions
No load, all outputs enabled
Output disabled
Clamp mode
Bias mode
All channels, DC
Min.
0.2
1.15
Typ.
80
2.8
3.0
0.3
1.25
50
Max
100
0.4
1.35
Units
mA
Vpp
kΩ
V
V
dB
AC Electrical Characteristics
Tc = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with
0.1uF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220uF into 150Ω
loads, referenced to 400kHz; unless otherwise noted.
Symbol
Parameter
AVSD
AVSTEP
f+1dB
f-1dB
fC
dG
Channel Gain1 Error
Gain Step1
1dB Peaking Bandwidth
-1dB Bandwidth
-3dB Bandwidth
Differential Gain
dP Differential Phase
THDSD
THDHD
XTALK1
XTALK2
XTALK3
XTALK4
XTALK5
SNRSD
VNOISE
AMPON
SD Output Distortion
HD Output Distortion
Input Crosstalk
Input Crosstalk
Output Crosstalk
Output Crosstalk
Multi-Channel Crosstalk
Signal-to-Noise Ratio5
Channel Noise
Amplifier Recovery Time
Conditions
All Channels, All Gain Settings, DC
All Channels, DC
VOUT = 1.4Vpp
VOUT = 1.4Vpp
VOUT = 1.4Vpp
3.58MHz
3.58MHz
VOUT = 1.4Vpp, 5MHz
VOUT = 1.4Vpp, 22MHz
1MHz, VOUT = 2Vpp2
15MHz, VOUT = 2Vpp2
1MHz, VOUT = 2Vpp3
15MHz, VOUT = 2Vpp3
Standard Video, VOUT = 2Vpp4
NTC-7 weighting, 4.2MHz LP, 100kHz HP
400kHz to 100MHz, Input referred
Post I2C programming
Min.
-0.2
0.9
Typ.
0
1
65
90
115
0.1
0.2
0.05
0.6
-72
-50
-68
-61
-45
73
20
300
Max
+0.2
1.1
Units
dB
dB
MHz
MHz
MHz
%
deg
%
%
dB
dB
dB
dB
dB
dB
nV/rtHz
ns
Notes:
1. 100% tested at 25°C.
2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch.
3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch.
4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output.
5. SNR = 20 * log (714mV / rms noise)
FMS6501 Rev. 1A
5 www.fairchildsemi.com
5 Page 
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6501DEMO, to use as a
guide for layout and to aid in device testing and characterization.
The FMS6501DEMO is a 4-layer board with a full power and
ground plane. For optimum results, follow the steps below as a
basis for high frequency layout:
• Include 10µF and 0.1µF bypass capacitors
• Place the 10µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Connect all external ground pins as tightly as possible, pref-
erably with a large ground plane under the package.
• Layout channel connections to reduce mutual trace induc-
tance
• Minimize all trace lengths to reduce series inductances. If
routing across a board, place device such that longer traces
are at the inputs rather than the outputs.
If using multiple, low impedance DC coupled outputs, special
layout techniques may be employed to help dissipate heat.
If a multilayer board is used, a large ground plane directly under
the device will help reduce package case temperature.
For dual layer boards, an extended plane can be used.
Worse case additional die power due to DC loading can be esti-
mated at (Vcc2/4Rload) per output channel. This assumes a con-
stant DC output voltage of Vcc/2. For 5V Vcc with a dual DC
video load, add 25/(4*75) = 83mW, per channel.
Applications for the FMS6501 Video Switch
Matrix
The increased demand for consumer multimedia systems has
created a large challenge for system designers to provide cost-
effective solutions to capitalize on the growth potential in graph-
ics display technologies. These applications will require cost
effective video switching and filtering solutions to deploy high-
quality display technologies rapidly and effectively to the target
audience. Areas of specific interest include HDTV, Media Cen-
ters, and Automotive Infotainment(includes navigation, in cabin
entertainment, and back up camera). In all cases, the advan-
tages the integrated video switch matrix provides are high qual-
ity video switching specific to the application as well as video
input clamps and on chip low impedance output cable drivers
with switchable gain.
Generally the largest application for a video switch is for the
front end of an HDTV. This is used to take multiple inputs and
route them to their appropriate signal paths (main picture and
picture in picture - PiP). These are normally routed into ADCs
that are followed by decoders. There are many different technol-
ogies for HDTV including: LCD,Plasma, and CRT that have sim-
ilar analog switching circuitry.
An example of a potential HDTV application is shown in figure 7
below. This system combines a video switch matrix and 2 -
three channel switchable anti-aliasing filters. This is done as
there are two 3-channel signal paths in the system - One is for
the main picture, and the other is the path for “Picture in Pic-
ture”.
VIPDEMOTM Control Software
The FMS6501 is configured via an I2C compatible digital inter-
face. In order to facilitate ease of demonstration, Fairchild Semi-
conductor had developed the VIPDEMOTM GUI based control
software to write to the FMS6501 register map. This software is
included when ordering an FMS6501DEMO kit. Also included is
a Parallel port I2C adapter and an interface cable to connect to
the demo board. Besides using the full FMS6501 interface, the
VIPDEMOTM can also be used to control single register read
and writes for I2C.
Figures 8 and 9 below show the control panel for the VIPDE-
MOTM control software and the FMS6501 device evaluation
board.
FMS6501 Rev. 1A
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet FMS6501.PDF ] | |
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