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IDT72V3652 fiches techniques PDF

IDT - (IDT72V3652 - IDT72V3672) 3.3 VOLT CMOS SyncBiFIFO

Numéro de référence IDT72V3652
Description (IDT72V3652 - IDT72V3672) 3.3 VOLT CMOS SyncBiFIFO
Fabricant IDT 
Logo IDT 





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IDT72V3652 fiche technique
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3.3 VOLT CMOS SyncBiFIFOTM
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3652
IDT72V3662
IDT72V3672
FEATURES
Memory storage capacity:
IDT72V3652 – 2,048 x 36 x 2
IDT72V3662 – 4,096 x 36 x 2
IDT72V3672 – 8,192 x 36 x 2
Supports clock frequencies up to 100MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723652/723662/723672
Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION
The IDT72V3652/72V3662/72V3672 are pin and functionally compatible
versions of the IDT723652/723662/723672, designed to run off a 3.3V supply
forexceptionallylow-powerconsumption. Thesedevicesaremonolithic,high-
speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which
support clock frequencies up to 100MHz and have read access times as fast
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
MBF1
36
FFA/IRA
AFA
FIFO 1
Status Flag
Logic
EFB/ORB
AEB
FS0
FS1
A0 - A35
EFA/ORA
AEA
Programmable Flag Timing
Offset Registers
Mode
13
FIFO 2
Status Flag
Logic
Read
Write
36
Pointer
Pointer
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FWFT
B0 - B35
FFB/IRB
AFB
36
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4660 drw01
NOVEMBER 2003
DSC-4660/3

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