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PDF 56F8025 Data sheet ( Hoja de datos )
| Número de pieza | 56F8025 | |
| Descripción | Digital Signal Controller Product Brief | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Product Brief
Document Number: MC56F8025PB
Rev. 0, 09/2006
56F8025 Digital Signal Controller
Product Brief
1 56F8025 Description
The 56F8025 is a member of the 56800E core-based
family of Digital Signal Controllers (DSCs). It
combines, on a single chip, the processing power of a
DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely
cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the
56F8025 is well-suited for many applications. The
56F8025 includes many peripherals that are especially
useful for industrial control, motion control, home
appliances, general-purpose inverters, smart sensors, fire
and security systems, switched-mode power supply,
power management, and medical monitoring
applications.
1
2
3
4
5
6
7
Contents
56F8025 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Digital Signal Controller Core . . . . . . . . . . . . . . . . . . . . . 3
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Peripheral Circuits for 56F8025. . . . . . . . . . . . . . . . . . . . 3
Recommended Operating Conditions . . . . . . . . . . . . . . . 5
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . 6
56F8025 Package and Pin-Out . . . . . . . . . . . . . . . . . . . . 7
The 56800E core is based on a dual Harvard-style
architecture consisting of three execution units operating
in parallel, allowing as many as six operations per
instruction cycle. The MCU-style programming model
and optimized instruction set allow straightforward
generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C
compilers to enable rapid development of optimized
control applications.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary—Subject to Change Without Notice
1 page  
Recommended Operating Conditions
— Output falling and rising edge detection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
• Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock sources:
— On-chip relaxation oscillator
— External clock: Crystal oscillator, ceramic resonator, and external clock source
• JTAG/EOnCE debug programming interface for real-time debugging
5 Recommended Operating Conditions
Table 1. Recommended Operating Conditions
(VREFL x= 0V, VSSA = 0V, VSS = 0V)
Characteristic
Symbol
Notes
Min Typ Max Unit
Supply voltage
ADC Reference Voltage High
Voltage difference VDD_IO to VDDA
Voltage difference VSS_IO to VSSA
Device Clock Frequency
Using relaxation oscillator
Using external clock source
Input Voltage High (digital inputs)
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
XTAL not driven by an external clock
XTAL driven by an external clock source
Oscillator Input Voltage Low
Analog Input Voltage
VDD,
VDDA
3 3.3 3.6
V
VREFHx
3.0
VDDA
V
ΔVDD
-0.1 0 0.1 V
ΔVSS
-0.3 0 0.3 V
FSYSCLK
1 32 MHz
0 32
VIH Pin Groups 1, 2 2.0
5.5 V
VIL Pin Groups 1, 2 -0.3
0.8 V
VIHOSC
Pin Group 4
VDDA - 0.8
2.0
VDDA + 0.3
VDDA + 0.3
V
VILOSC
Pin Group 4
-0.3
0.8 V
VIA Pin Group 3 0.0
VDDA
V
Freescale Semiconductor
56F8025 Digital Signal Controller Product Brief, Rev. 0
Preliminary—Subject to Change Without Notice
5
5 Page 
THIS PAGE IS INTENTIONALLY BLANK
Freescale Semiconductor
56F8025 Digital Signal Controller Product Brief, Rev. 0
Preliminary—Subject to Change Without Notice
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 56F8025.PDF ] | |
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