PDF ZL30414 Data sheet ( Hoja de datos )

Número de pieza	ZL30414
Descripción	SONET/SDH Clock Multiplier PLL
Fabricantes	Zarlink Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de ZL30414 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas
No Preview Available ! www.DataSheet4U.com ZL30414 SONET/SDH Clock Multiplier PLL Features • Meets jitter requirements of Telcordia GR-253- CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM- 64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at 622.08 MHz • Provides a CML differential clock at 155.52 MHz • Provides a single-ended CMOS clock at 19.44 MHz • Lock Indicator • Provides enable/disable control of output clocks • Accepts a CMOS reference at 19.44 MHz • 3.3 V supply Applications • SONET/SDH line cards • Network Element timing cards Data Sheet February 2005 Ordering Information ZL30414QGC 64 Pin TQFP Trays ZL30414QGC1 64 Pin TQFP* Trays *Pb Free Matte Tin -40°C to +85°C Description The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC- 3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates. The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. The ZL30414 provides a LOCK indication. C19i C622oEN-A C622oEN-B LPF C622oEN-C C622oEN-D Frequency & Phase Detector Loop Filter State Machine Reference and Bias Circuit LOCK BIAS VCO 19.44MHz Frequency Dividers and Clock Drivers C622oP/N-A C622oP/N-B C622oP/N-C C622oP/N-D C155oP/N C19o VDD GND VCC C155oEN C19oEN Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. 05 1 page ZL30414 Data Sheet Pin Description Table (continued) Pin # 60 61 62 63 64 65 Name GND VCC C622oP-A C622oN-A GND NC Description Ground. 0 volt Positive Analog Power Supply. +3.3 V ±10%. C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt No internal bonding Connection. Leave unconnected. 1.0 Functional Description The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections. 1.1 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit. 1.2 Lock Indicator The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds ±1000 ppm. 1.3 Loop Filter The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown in Figure 3. Frequency and Phase Detector VCO ZL30414 Loop Filter LPF RF CF RF=8.2 kΩ, CF=470 nF Figure 3 - Loop Filter Elements 5 Zarlink Semiconductor Inc. 5 Page ZL30414 Data Sheet 3.2 Recommended Interface circuit 3.2.1 LVPECL to LVPECL Interface The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at 622.08 MHz. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver. +3.3 V ZL30414 VCC LVPECL Driver 622.08 MHz GND C622oP-A C622oN-A 0.1 uF Z=50 Ω Z=50 Ω VCC=+3.3 V R1 R1 LVPECL Receiver R2 R2 Typical resistor values: R1 = 130 Ω, R2 =82 Ω Figure 8 - LVPECL to LVPECL Interface 3.2.2 CML to CML Interface The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a 50 Ω load at the terminating end if the receiver is CML type. +3.3 V ZL30414 VCC CML Driver 155.52 MHz GND C155oP C155oN 0.1 uF 0.1 uF Z=50 Ω Z=50 Ω 0.1 uF Low impedance DC bias source 50 Ω 50 Ω CML Receiver Figure 9 - CML to CML Interface 11 Zarlink Semiconductor Inc. 11 Page

Páginas	Total 24 Páginas
PDF Descargar	[ Datasheet ZL30414.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ZL30410	Multi-service Line Card PLL	Zarlink Semiconductor
ZL30414	SONET/SDH Clock Multiplier PLL	Zarlink Semiconductor
ZL30415	SONET/SDH Clock Multiplier PLL	Zarlink Semiconductor
ZL30416	SONET/SDH Clock Multiplier PLL	Zarlink Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar